Method and system for impedance matched switching

• US 6,903,596 B2
• Filed: 03/17/2003
• Issued: 06/07/2005
• Est. Priority Date: 03/17/2003
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Electric & Electronics USA Incorporated (Mitsubishi Electric Corporation)
• Inventors: Shaw, Daniel, Geller, Bernard, Metheny, Glen C.
• Primary Examiner(s): NGUYEN, MINH T
• Application Number:
  US10/388,459
• Publication Number:
  US 20040183623A1
• Time in Patent Office: 813 Days
• Field of Search: 327/308, 327/419, 327/427, 327/365, 327/374, 333/101, 333/103, 333/81.A, 333/81.R, 333/262
• US Class Current: 327/427
• CPC Class Codes: H01P 1/15 by semiconductor devices

Abstract

A system for impedance matched switching of an input signal from an input source includes a first switch, such as an FET, for controllably switching the input signal from an input terminal connected to the input source to an output terminal, the switching being controlled according to a control voltage. The system further includes a second switch, such as an FET, for controllably switching a matching impedance between the input terminal and ground according to the control voltage. When the input signal is prevented from passing from the input terminal to the output terminal by the first switch, the input signal passes through the matching impedance, which has an impedance characteristic substantially matched to an impedance characteristic of the input source.

Claims

1. A system for impedance matched switching of an input signal from an input source, the system comprising:

first means for controllably switching the input signal from an input terminal connected to the input source to an output terminal, said switching controlled according to a control voltage; and

second means for controllably switching a matching impedance means between the input terminal and ground according to the control voltage, wherein when the input signal is prevented from passing from the input terminal to the output terminal by the first means for controllably switching, the input signal passes through the matching impedance means, said matching impedance means having an impedance characteristic substantially matched to an impedance characteristic of the input source.

2. The system of claim 1, wherein at least one of the first and second means for controllably switching comprises a FET.

3. The system of claim 1, wherein at least one of the first and second means for controllably switching comprises a depletion-mode FET.

4. The system of claim 1, wherein the matching impedance means comprises a high value biasing resistor and a lower value resistor that are connected in parallel when said second switching means is actuated, the parallel combination of the two resistors having an impedance characteristic substantially matched to the impedance characteristic of the input source.

5. The system of claim 1, wherein the first means for controllably switching is coupled to the input terminal via a first coupling capacitor and to the output terminal via a second coupling capacitor.

6. A system for impedance matched switching of a plurality of input signals, each from a respective plurality of input sources, to a common output terminal, the system comprising:

a plurality of switching circuits each having their respective output terminal connected to the common output, each switching circuit comprising;

first means for controllably switching the input signal from an input terminal connected to the input source to an output terminal connected to the common output, said switching controlled according to a control voltage; and

second means for controllably switching a matching impedance means between the input terminal and ground according to the control voltage, wherein when the input signal is prevented from passing from the input terminal to the output terminal by the first means for controllably switching, the input signal passes through the matching impedance means, said matching impedance means having an impedance characteristic substantially matched to an impedance characteristic of the input source.

7. The system of claim 6, wherein at least one of the first and second means for controllably switching comprises a FET.

8. The system of claim 6, wherein at least one of the first and second means for controllably switching comprises a depletion-mode FET.

9. The system of claim 6, wherein the matching impedance means comprises a high value biasing resistor and a lower value resistor that are connected in parallel when said second switching means is actuated, the parallel combination of the two resistors having an impedance characteristic substantially matched to the impedance characteristic of the input source.

10. The system of claim 6, wherein the first means for controllably switching is coupled to the input terminal via a first coupling capacitor and to the output terminal via a second coupling capacitor.

11. A method for impedance matched switching of an input signal from an input source, the method comprising the steps of:

controllably switching the input signal from an input terminal connected to the input source to an output terminal, said switching controlled according to a control voltage; and

controllably switching a matching impedance means between the input terminal and ground according to the control voltage, wherein when the input signal is prevented from passing from the input terminal to the output terminal by the first means for controllably switching, the input signal passes through the matching impedance means, said matching impedance means having an impedance characteristic substantially matched to an impedance characteristic of the input source.

12. A circuit for impedance matched switching of an input signal from an input source, the circuit comprising:

a first FET coupled to the input terminal via a first coupling capacitor and coupled to the output terminal via a second coupling capacitor, wherein a source terminal and a drain terminal of the first FET are each coupled to a positive potential via respective first and second biasing resistors and a gate terminal of the first FET is coupled to a control voltage via a first gate resistor; and

a second FET having a drain terminal coupled, via a third coupling capacitor, to a connection between the first FET and the first coupling capacitor, the drain terminal also coupled to the control voltage via a high impedance biasing resistor, a source terminal of the second FET being coupled to the control voltage via an impedance matching biasing resistor, the control voltage being coupled to ground at a junction of the high impedance biasing resistor, the impedance matching biasing resistor, and the first gate resistor via a fourth coupling capacitor, and a gate terminal of the second FET being coupled to ground via a second gate resistor,

wherein a combined impedance characteristic of the high impedance biasing resistor and the impedance matching biasing resistor is substantially matched to an impedance characteristic of the input source.