Method and apparatus for synthesizing high-frequency signals for wireless communications

• US 6,903,617 B2
• Filed: 02/22/2002
• Issued: 06/07/2005
• Est. Priority Date: 05/25/2000
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Lim, Lysander, Welland, David R., Pavelka, John B., Healy, Edmund G.
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US10/081,730
• Publication Number:
  US 20020163396A1
• Time in Patent Office: 1,201 Days
• Field of Search: 331/117.R, 331/151, 331/15, 331/18, 331/36.L, 331/17, 331/16, 331/1.A, 331/2, 331/31
• US Class Current: 331/151
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/104 : using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/199 : with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Abstract

A semiconductor package includes a package substrate and an integrated circuit. The package substrate has a first surface. The integrated circuit couples electrically to the first surface of the package substrate. The integrated circuit and the package substrate together form the semiconductor package. The semiconductor package also includes a first inductance circuit and a second inductance circuit, both formed within the semiconductor package. The first and second inductance circuits couple to each other in parallel. The first and second inductance circuits have substantially symmetrical geometric characteristics.

Claims

1. A method of assembling a semiconductor package, comprising:

providing a package substrate having a first surface;

including within the semiconductor package an integrated circuit electrically coupled to the package substrate;

forming a first inductor within the semiconductor package, the first inductor being formed at least partially between the integrated circuit and the package substrate; and

forming a second inductor within the semiconductor package, the second inductor being formed at least partially between the integrated circuit and the package substrate, the second inductor being coupled electrically in parallel with the first inductor,

wherein the first and second inductors are formed within the semiconductor package so that an interfering magnetic signal induces a common-mode signal in the parallel combination of the first and second inductors.

2. The method according to claim 1, wherein forming the first inductor further comprises:

providing a first substrate electrical contact on the first surface of the package substrate; and

coupling electrically first and second conductive features between the integrated circuit and the first substrate electrical contact to form an electrically conductive path.

3. The method according to claim 2, wherein forming the second inductor further comprises:

providing a second substrate electrical contact on the first surface of the package substrate; and

coupling electrically third and fourth conductive features between the integrated circuit and the first substrate electrical contact to form an electrically conductive path.

4. The method according to claim 3, wherein forming the first inductor further comprises:

including within the package substrate a first set of at least two alternative substrate electrical contacts corresponding to the first inductor to provide alternate electrical connection points during package assembly for at least one or both of the first and second conductive features of the first inductor,

wherein an inductance value of the first inductor depends on the identity of the alternative substrate electrical contact selected in the first set of at least two alternative substrate electrical contacts for coupling electrically to at least one or both of the first and second conductive features.

5. The method according to claim 4, wherein forming the second inductor further comprises:

including within the package substrate a second set of at least two alternative substrate electrical contacts corresponding to the second inductor to provide alternate electrical connection points during package assembly for at least one or both of the third and fourth conductive features of the second inductor,

wherein an inductance value of the second inductor depends on the identity of the alternative substrate electrical contact selected in the second set of at least two alternative substrate electrical contacts for coupling electrically to at least one or both of the third and fourth conductive features.

6. The method according to claim 5, wherein the first set of alternative substrate electrical contacts comprises alternative substrate bonding pads disposed at variable distances from the integrated circuit, and wherein the first and second conductive features of the first inductor comprise first and second wire bonds electrically coupled to a selected one of the alternative substrate bonding pads to form an electrically conductive path having an inductance value at least partially dependent on at least one of the lengths of the first and second wire bonds, the distance between the first and second wire bonds, or both.

7. The method according to claim 6, wherein the second set of alternative substrate electrical contacts comprises alternative substrate bonding pads disposed at variable distances from the integrated circuit, and wherein the third and fourth conductive features of the second inductor comprise third and fourth wire bonds electrically coupled to a selected one of the alternative substrate bonding pads to form an electrically conductive path having an inductance value at least partially dependent on at least one of the lengths of the third and fourth wire bonds, the distance between the third and fourth wire bonds, or both.

8. The method according to claim 5, wherein the first set of alternative substrate electrical contacts corresponding to the first inductor comprises alternative pairs of first and second substrate bonding pads positioned at variable locations on or within the package substrate, each of the first and second substrate bonding pads of a bonding pad pair being electrically coupled to one another on or within the package substrate by a fifth conductive feature, and wherein the first and second conductive features of the first inductor comprise first and second solder bumps positioned so that they are electrically coupled to a selected respective alternative pair of first and second substrate bonding pads to form an electrically conductive path.

9. The method according to claim 8, wherein the second set of alternative substrate electrical contacts corresponding to the second inductor comprises alternative pairs of third and fourth substrate bonding pads positioned at variable locations on or within the package substrate, each of the third and fourth substrate bonding pads of a bonding pad pair being electrically coupled to one another on or within the package substrate by a sixth conductive feature, and wherein the third and fourth conductive features of the second inductor comprise third and fourth solder bumps positioned so that they are electrically coupled to a selected respective alternative pair of third and fourth substrate bonding pads to form an electrically conductive path.

10. The method according to claim 5, wherein the first set of alternative substrate electrical contacts corresponding to the first inductor comprises alternative pairs of first and second substrate bonding pads positioned at variable locations on or within the package substrate, each of the first and second substrate bonding pads of a bonding pad pair being electrically coupled to one another on or within the package substrate by a fifth conductive feature, and wherein the first and second conductive features of the first inductor comprise first and second wire bonds electrically coupled to a selected respective alternative pair of first and second substrate bonding pads to form an electrically conductive path.

11. The method according to claim 10, wherein the second set of alternative substrate electrical contacts corresponding to the second inductor comprises alternative pairs of third and fourth substrate bonding pads positioned at variable locations on or within the package substrate, each of the third and fourth substrate bonding pads of a bonding pad pair being electrically coupled to one another on or within the package substrate by a sixth conductive feature, and wherein the third and fourth conductive features of the second inductor comprise third and fourth wire bonds electrically coupled to a selected respective alternative pair of third and fourth substrate bonding pads to form an electrically conductive path.

12. The method according to claim 5, further comprising providing a phase locked loop circuit within the integrated circuit, the phase locked loop circuit being electrically coupled to the first and second inductors.

13. The method according to claim 12, further comprising including a controlled oscillator circuit within the phase locked loop circuit.

14. The method according to claim 13, wherein the controlled oscillator circuit has an output frequency that is selectably operable within a plurality of frequency bands.

15. The method according to claim 14, wherein the controlled oscillator circuit comprises an inductor-capacitor tank circuit.

16. The method according to claim 15, wherein the inductor-capacitor tank circuit comprises a capacitor electrically coupled to the first and second inductors.

17. The method according to claim 16, wherein the first and second inductors are formed entirely within the semiconductor package.

18. The method according to claim 5, wherein the first and second inductors are formed symmetrically with respect to each other.