Circuit and method for cancellation of column pattern noise in CMOS imagers
First Claim
1. A method for compensating non-linearity errors in A/D converter conversion operations associated with converting analog image data from a CMOS imager to digital data, comprising:
- (a) isolating an A/D converter from the CMOS imager;
(b) applying a plurality of analog voltages to the isolated A/D converter, the plurality of voltages ranging from analog ground to a full-scale voltage level;
(c) measuring and storing a difference between an output from the isolated A/D converter and a reference value associated with the analog voltage being applied to the isolated A/D converter; and
(d) correcting the non-linearity of the isolated the isolated A/D converter using the stored difference.
2 Assignments
0 Petitions
Accused Products
Abstract
A circuit and method measure the output voltage of a CMOS pixel in a manner that substantially reduces all columnar pattern noise due to mismatches in the signal processing circuits including the correlated double sampling amplifiers and A/D converters. The circuit includes a test switch, operatively connected between a reference voltage source and a correlated double sampling amplifier, for applying a test voltage from the reference voltage source when the state of the test switch is ON to the correlated double sampling amplifier. The reference voltage source produces a voltage corresponding to a full-scale voltage level to enable the determination of a gain error in the correlated double sampling amplifier and/or A/D converter; a voltage corresponding to ground to enable the determination of an offset error in the correlated double sampling amplifier and/or A/D converter; and a plurality of analog voltages ranging from analog ground to a full-scale voltage level to enable the determination of non-linearity errors in the A/D converter.
-
Citations
12 Claims
-
1. A method for compensating non-linearity errors in A/D converter conversion operations associated with converting analog image data from a CMOS imager to digital data, comprising:
-
(a) isolating an A/D converter from the CMOS imager;
(b) applying a plurality of analog voltages to the isolated A/D converter, the plurality of voltages ranging from analog ground to a full-scale voltage level;
(c) measuring and storing a difference between an output from the isolated A/D converter and a reference value associated with the analog voltage being applied to the isolated A/D converter; and
(d) correcting the non-linearity of the isolated the isolated A/D converter using the stored difference. - View Dependent Claims (2)
-
-
3. A circuit for compensating errors in correlated double sampling amplifiers and/or A/D converters associated with a CMOS imager having columns of pixels, comprising:
-
a reference voltage source to produce test voltages;
a test switch operatively connected between said reference voltage source and a correlated double sampling amplifier;
a test switch control line, operatively connected to said test switch, to apply a signal to said test switch, said signal controlling an ON/OFF state of said test switch, said test switch applying a test voltage from said reference voltage source to the correlated double sampling amplifier when the state of said test switch is ON; and
a measurement circuit to measure a difference between an output of the A/D converter produced from a test voltage being applied to the correlated double sampling amplifier through said test switch and a reference voltage associated with the applied test voltage to determine an error in the correlated double sampling amplifier and/or A/D converter. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12)
-
Specification