Method and apparatus for multi-display of digital visual interfaces

• US 6,903,706 B1
• Filed: 03/20/2002
• Issued: 06/07/2005
• Est. Priority Date: 03/20/2002
• Status: Active Grant

• Current Assignee: Matrox Graphics Incorporated (Matrox Electronic Systems Ltd.)
• Original Assignee: Matrox Graphics Incorporated (Matrox Electronic Systems Ltd.)
• Inventors: Lafleur, Robert, Tremblay, Yves, Samdjy, Razid, Tremblay, Stéphane, Trottier, Lorne
• Primary Examiner(s): Shankar, Vijay
• Assistant Examiner(s): Dharia, Prabodh M
• Application Number:
  US10/101,503
• Time in Patent Office: 1,175 Days
• Field of Search: 345/1.1, 345/1.3, 345/212, 345/698, 345/545, 345/1, 345/102, 345/207, 345/208, 345/150, 345/154, 345/88, 345/3.1, 345/211, 345/217, 345/147, 345/543, 345/903, 375/295, 375/260, 375/316, 348/231.99, 349/106, 356/244, 359/618, 342/26, 370/521, 713/189, 358/22, 725/74
• US Class Current: 345/1.1
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

Provides an apparatus and method for displaying dual Digital Visual Interface (DVI) displays simultaneously, with independent images, by using a Transition Minimized Differential Signaling (TMDS) serializer with dual channels and one clock. Also provides an apparatus and method allowing either two low-resolution displays or one high-resolution display to be driven by a reduced circuit.

Claims

1. An apparatus for providing output to at least two digital displays, said apparatus comprising:

a serializer having a first channel and a second channel, a first pixel input a second pixel input, first pixel output, second pixel output, and a serializer clock controlling said first and second channels, synchronized with a pixel clock signal and having an output adapted to feed at least two digital displays over separate channels;

a first display controller output carrying a first display pixel stream connected to said first pixel input;

a second display controller output carrying a second display pixel stream connected to said second pixel input, said first and said second display pixel streams synchronized according to said pixel clock signal;

a first digital display connector operatively connected between said first pixel output, said serializer clock output, and a first single link digital display; and

a second digital display connector operatively connected between said second pixel output, said serializer clock output, and a second single link digital display.

2. An apparatus as claimed in claim 1, said apparatus further comprising:

a first encoder having an input being selectively one of said first display pixel stream and said second display pixel stream and an output operatively connected to said first channel of said serializer; and

a second encoder having as input said second display pixel stream and an output operatively connected to said second channel of said serializer.

3. An apparatus as claimed in claim 1, further comprising an external clock signal amplifier circuit to amplify a clock signal from said serializer clock so as to provide said first digital display and said second digital display with an essentially undistorted clock signal.

4. An apparatus as claimed in claim 1, further comprising:

a primary requester to generate said first display pixel stream;

an overlay requester to generate said second display pixel stream;

a blender unit receiving an output from said primary requestor and an output from said overlay requestor and producing a blended output, wherein said blended output is said first display controller output;

wherein said output from said overlay requestor is also said second display controller output and said primary requestor and said secondary requester are driven by said pixel clock.

5. An apparatus as claimed in claim 1, wherein said serializer clock further comprises a first pixel clock output and a second pixel dock output, said first pixel clock output operatively connected to said first digital display connector and said second pixel clock output operatively connected to said second digital display connector.

6. An apparatus as claimed in claim 2, further comprising:

a first clock bridge circuit that synchronizes said first digital display pixel stream from a first clock rate to a second clock rate;

a second clock bridge circuit that synchronizes said second digital display pixel stream from a first clock rate to a second clock rate;

a hold control circuit to control said first encoder, said second encoder, said first clock bridge circuit, and said second clock bridge circuit, wherein said hold control circuit sends a hold signal indicating that data is to be held for a clock cycle; and

a multiplexor to selectively transmit to said second encoder at least one of said first display pixel stream and said second display pixel stream.

7. An apparatus as claimed in claim 6, further comprising a third digital display connector operatively connected between said first pixel output, said second pixel output, said pixel clock, and a dual link digital display.

8. An apparatus as claimed in claim 4, further comprising:

a first clock bridge circuit that synchronizes said first digital display pixel stream from a first clock rate to a second clock rate;

a second clock bridge circuit that synchronizes said second digital display pixel stream from a first clock rate to a second clock rate;

a hold control circuit to control said first encoder, said second encoder, said first clock bridge circuit, and said second clock bridge circuit, wherein said hold control circuit sends a hold signal indicating that data is to be held for a clock cycle; and

a multiplexor to selectively transmit to said second encoder at least one of said first display pixel stream and said second display pixel stream.

9. An apparatus as claimed in claim 6, further comprising an external clock signal amplifier circuit to amplify a clock signal from said serializer clock, so as to provide said first digital display and said second digital display with an essentially undistorted clock signal.

10. An apparatus as claimed in claim 6, wherein said serializer clock further comprises a first pixel clock input, a second pixel clock input, a first pixel clock output and a second pixel clock output, said first pixel clock output operatively connected to said first digital display connector and said second pixel clock output operatively connected to said second digital display connector.

11. An apparatus for providing output to at least two digital displays, said apparatus comprising:

a serializer having a first channel and a second channel, first pixel input, a second pixel input, a first pixel output, a second pixel output, and serializer clock circuitry synchronized with a pixel clock signal and having output for at least two digital displays;

a first display controller output carrying a first display pixel stream connected to said first, pixel input;

a second display controller output carrying a second display pixel stream connected to said second pixel input, said first and said second display pixel streams being synchronized according to said pixel clock signal;

a first clock bridge circuit that synchronizes said first digital display pixel stream from a first clock rate to a second clock rate;

a second clock bridge circuit that synchronizes said second digital display pixel stream from a first clock rate to a second clock rate;

a hold control circuit to control said first clock bridge circuit, and said second clock bridge circuit, wherein said hold control circuit sends a hold signal indicating that data is to be held for a clock cycle;

a multiplexor to selectively transmit to said second channel at least one of said first display pixel stream and said second display pixel stream; and

a digital display connector operatively connected to said first pixel output, said second pixel output, and said serializer clock output.

12. A method for driving at least two digital displays with independent images, said method comprising:

providing a serializer having two separate channels and a serialized clock controlling said channels, synchronized with a pixel clock signal, and having an output adapted to feed at least two digital display;

transmitting data along at least two buses to said serializer,

serializing said data using said serializer;

transmitting serialized data from said channels and said serializer clock output via cables to said at least two digital display.

13. A method for selectively driving one of two digital displays with independent images and one higher resolution digital display, said method comprising:

channeling pixel data along two buses to a serializer having two channels in accordance with a selected one of two display modes;

serializing said data using said serializer;

transmitting serialized date from said channels and a serializer clock to one of;

said two digital displays and said higher resolution digital display, in accordance with said selected one of two display modes.

14. A method as claimed in claim 13, further comprising:

providing a connector for said serialized data and said serializer clock signal from said channels; and

selectively connecting one of a bifurcated cable having a first end going into said connector, a first display end going into a first one of said two digital displays, and a second display end going into a second one of said two digital displays, and a non-bifurcated cable having a first end going into said connector and a second end going into said higher resolution digital display.