Clip-on leadframe for large ceramic SMD

• US 6,903,920 B1
• Filed: 08/06/2004
• Issued: 06/07/2005
• Est. Priority Date: 08/06/2004
• Status: Active Grant

• Current Assignee: Kemet Electronics Corporation (Yageo Corporation)
• Original Assignee: Kemet Electronics Company Limited (Yageo Corporation)
• Inventors: Prymak, John D.
• Primary Examiner(s): Reichard, Dean A.
• Assistant Examiner(s): Ha, Nguyen T.
• Application Number:
  US10/913,767
• Time in Patent Office: 305 Days
• Field of Search: 361/321.2, 361/321.1, 361/321.5, 361/301.4, 361/306.1, 361/306.3, 361/308.1, 361/310, 361/311, 361/313, 361/320, 361/322, 361/328
• US Class Current: 361/321.2
• CPC Class Codes: H01G 2/065 for surface mounting, e.g. chip capacitors
• CPC Class Codes: H01G 4/248 the terminals embracing or surrounding the capacitive element, e.g. caps H01G4/252 takes precedence
• CPC Class Codes: H05K 3/3426 characterised by the leads
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A ceramic capacitor with a low-profile leadframe. The ceramic capacitor comprises a multiplicity of parallel plates in planar relationship. Each plate terminates at opposing faces in an alternating pattern. A dielectric is between the parallel plates. Two external terminations are on opposing sides of the capacitor wherein each external termination is in electrical contact with alternating plates of the multiplicity of parallel plates. The bottom half of the ceramic capacitor including the external terminations is treated with an insulative coating prior to attachment to a leadframe. The noninsulated portions of the terminations are attached to the leadframe and the insulator prevents the leadframe from attaching to the lower vertical faces of the terminations. The leadframe in this manner creates no excessive distance between the chip and the PCB surface, thus reducing inductance and resistance.

Claims

1. A ceramic capacitor comprising:

a multiplicity of parallel plates in planar relationship wherein each plate terminates at an opposing faces in an alternating pattern;

a dielectric between said parallel plates;

two external terminations on opposing sides of said capacitor wherein a first external termination is in electrical contact with alternating plates of said multiplicity of parallel plates and a second external termination is in electrical contact with separate alternating plates than said first external termination;

an insulator covering a portion of said two external terminations;

a first low-profile lead terminal in electrical contact with said first external termination at a location void of said insulator; and

a second low-profile lead terminal in electrical contact with said second external termination at a location void of said insulator.

2. The ceramic capacitor of claim 1 wherein said insulation is between said first external termination and a first foot of said first low-profile lead and between said second external termination and a second foot of said second low-profile lead.

3. The ceramic capacitor of claim 2 wherein said insulator is in contact with said first external termination and said first foot.

4. The ceramic capacitor of claim 1 wherein said insulator covers at least one fourth of the surface of said external leads.

5. The ceramic capacitor of claim 4 wherein said insulator covers at least one half of the surface of said external leads.

6. The ceramic capacitor of claim 5 wherein said low-profile lead frame is in electrical contact with a top of said external lead.

7. A printed circuit board further comprising a capacitor of claim 1.

8. The printed circuit board of claim 7 wherein said capacitor is attached to said printed circuit board by a solder strip.