Method of writing to an organic memory

• US 6,903,958 B2
• Filed: 09/05/2001
• Issued: 06/07/2005
• Est. Priority Date: 09/13/2000
• Status: Expired due to Fees

• Current Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Original Assignee: Siemens AG
• Inventors: Fix, Walter, Lorenz, Markus, Rost, Henning, Bernds, Adolf, Clemens, Wolfgang
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/380,206
• Publication Number:
  US 20040026690A1
• Time in Patent Office: 1,371 Days
• Field of Search: 365/96, 365/105, 365/115, 365/151, 257/40
• US Class Current: 365/96
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards

Abstract

The invention relates to a memory, based on organic material and applied in combination with an organic integrated circuit (integrated plastic circuit). The invention particularly relates to a memory for a RFID-Tag (RFID-tags: radio frequency identification tags) and several methods for describing a memory.

Claims

1. Method for writing to an organic memory, comprising the steps of:

providing at least one integrated circuit comprising a plurality of transistors each based on organic material wherein a transistor active element comprises mainly organic material; and

selectively setting each said transistor to be one of conductive and non conductive;

wherein said selective setting is accomplished by at least one of controlling the presence or absence of one or more selected transistors within the integrated circuits such that the one or more selected transistors are made nonconducting through manipulation of one or more conductor tracks, and single conductor tracks are arranged to be conducting or non-conducting.

2. Method according to claim 1, wherein the selective setting is performed by mask programming in which the selected transistors or gate of the selected transistors are not present at corresponding locations.

3. Method according to claim 2, wherein a change in a dielectric constant in the integrated circuit is implemented by laser light.

4. Method according to claim 2, wherein the write process is implemented by fusible links.

5. Method according to claim 2, wherein the transistors each include a conductor track, and a conductor track is destroyed by means of one of laser light and specifically applied heat, and thus rendered non-conducting.

6. Method according to claim 2, wherein the transistors each include a conductor track, and mechanical processing is used to manipulate a conductor track.

7. Method according to claim 1, wherein the selective setting is implemented using fusible links.

8. Method according to claim 7, wherein the transistors each include a conductor track, and a conductor track is destroyed by means of one of laser light and specifically applied heat, and thus rendered non-conducting.

9. Method according to claim 7, wherein the transistors each include a conductor track, and mechanical processing is used to manipulate a conductor track.

10. Method according to claim 1, wherein the transistors each include a conductor track, and the conductor track is destroyed by means of one of laser light and specifically applied heat, and thus rendered non-conducting.

11. Method according to claim 10, wherein the transistors each include a conductor track, and mechanical processing is used to manipulate a conductor track.

12. Method according to claim 1, wherein chemical treatment is used to change conductivity of selected areas of the one or more selected transistors.

13. The method of claim 12, wherein the chemical treatment comprises use of a base/acid stamp.

14. Method according to claim 12, wherein the transistors each include a conductor track, and mechanical processing is used to manipulate a conductor track.

15. Method according to claim 1, wherein the transistors each include a conductor track, and mechanical processing is used to manipulate a conductor track.

16. Method according to claim 1, wherein the transistors each include a conductor track, and an electrical voltage is used to locally short-circuit a conductor track.

17. Method according to claim 1, wherein the transistors each include a conductor track, and a conductor track is separated or closed on a mask by omitting a structure during the providing.

18. Method according to claim 1, wherein the method is used in order to impress a particular bit arrangement.

19. The method of claim 1, wherein each transistor has a gate oxide, selective setting being performed by mask programming to control conductivity of the selected one or more transistors by adjusting a dielectric constant of the gate oxide of each said selected transistor.

20. The method of claim 1, wherein the transistors each include a conductor track, and electrical voltage is used to destroy a conductor track through overheating.