Apparatus and methods for storing and processing header information in a network switch

• US 6,904,043 B1
• Filed: 05/21/1999
• Issued: 06/07/2005
• Est. Priority Date: 05/21/1999
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Ching, Merchant, Shashank
• Primary Examiner(s): LUTHER, WILLIAM A
• Application Number:
  US09/316,072
• Time in Patent Office: 2,209 Days
• Field of Search: 370/389, 370400-401, 370/402, 370412-413, 370/419, 370/428, 370/429
• US Class Current: 370/402
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A network switch configured for switching data packets across multiple ports uses an internal memory to store frame headers for processing by decision making logic. The internal memory stores frame headers in a queue configured to store a number of the frame headers for each of the receive ports. A scheduler is included for facilitating the transfer the data from the queues to the decision making logic according to a predetermined priority. The scheduler is also able allocate the time slots in accordance with data traffic at the corresponding receive ports to maximize data throughput.

Claims

1. A multiport switch configured for controlling communication of data frames between stations, comprising:

a plurality of receive devices corresponding to ports on the multiport switch, each of the receive devices configured to receive data frames and transmit the data frames on an internal bus to an external memory interface;

a plurality of queues corresponding to ports on the multiport switch, the plurality of queues formed on a memory device that includes a write port and a read port to enable data to be written to and read from the memory device simultaneously, wherein each of the plurality of queues is configured to store frame header information received via the write port;

a scheduler configured to allocate time slots to the plurality of queues;

a decision making engine configured to receive the frame header information in successive time slots via the read port and to generate data forwarding information; and

a read controller configured to transfer frame header information from the plurality of queues to the decision making engine via the read port,

wherein the scheduler is configured to allocate the time slots based on a predetermined priority and the read controller is configured to transmit frame header information to the decision making engine during the allocated time slots.

2. The multiport switch of claim 1, wherein the read controller is configured to transmit a request signal to the scheduler, the request signal indicating that a first queue has stored frame header information.

3. The multiport switch of claim 2, wherein:

each of the plurality of queues is assigned at least one time slot in a scheduling cycle and the scheduler is configured to allocate the time slot assigned to the first queue when a request signal associated with the first queue has been received, and

the read controller is configured to transmit the frame header information from the first queue to the decision making engine during the allocated time slot.

4. The multiport switch of claim 1, wherein the frame header information comprises a source address and destination address of the data frame.

5. The multiport switch of claim 4, wherein the frame header information includes virtual local area network (VLAN) information.

6. The multiport switch of claim 1, wherein the memory device comprises a plurality of synchronous random access memory (SRAM) devices and each SRAM device includes a write port and a read port to enable data to be written to and read from each SRAM device simultaneously.

7. In a multiport switch that controls communication of data frames between stations and includes a plurality of queues corresponding to ports on the multiport switch, a method of processing data frames, comprising:

receiving data frames at a plurality of receive devices;

transmitting the data frames to an external memory interface;

writing frame header information from the data frames to a plurality of queues corresponding to the plurality of receive devices, wherein the plurality of queues are formed on a memory device that includes a write port and a read port;

allocating time slots to the plurality of queuing devices;

transmitting the frame header information from the queues, via the read port and in successive time slots, to an internal decision making engine;

generating data forwarding information;

allocating time slots based on a predetermined priority;

transmitting frame header information during the allocated time slots; and

transmitting a request signal to a scheduler, the request signal indicating that a first queue has stored frame header information.

8. The method of claim 7, comprising:

assigning at least one time slot in a scheduling cycle to cach of the plurality of queues; and

allocating the time slot assigned to a first queue when the request signal has been received.

9. The method of claim 7, wherein the frame header information comprises a source address and a destination address of the data frame.

10. The method of claim 7, wherein the frame header information comprises virtual local area network (VLAN) information.

11. A multiport switch configured for controlling communication of data frames between stations, comprising:

a plurality of receive devices corresponding to ports on the multiport switch, each of the receive devices configured to receive data frames and transmit the data frames on an internal bus to an external memory interface;

a plurality of queues corresponding to ports on the multiport switch, the plurality of queues formed on a memory device that includes a write port and a read port, wherein each of the plurality of queues is assigned at least one time slot in a scheduling cycle and is configured to store frame header information via the write port;

a scheduler configured to allocate time slots to the plurality of queues based on data traffic at the corresponding receive ports;

a decision making engine configured to receive the frame header information in successive time slots via the read port and to generate data forwarding information; and

a memory controller configured to transfer frame header information from the plurality of queues to the decision making engine via the read port,

wherein the scheduler is configured to allocate the time slots based on a predetermined priority and the read controller is configured to transmit frame header information to the decision making engine during the allocated time slots.

12. The multiport switch of claim 11, wherein:

the memory controller is configured to transmit a request signal to the scheduler, the request signal indicating that a first queue has stored frame header information,

the scheduler is configured to allocate a time slot assigned to the first queue when the request signal has been received, and

the memory controller is configured to transmit the frame header information from the first queue to the decision making engine during the allocated time slot.

13. The multiport switch of claim 11, wherein

the frame header information comprises a source address, and a destination address of the data frame.