Method and system of managing virtualized physical memory in a multi-processor system

• US 6,904,490 B2
• Filed: 10/10/2002
• Issued: 06/07/2005
• Est. Priority Date: 10/10/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ghai, Sanjeev, Arimilli, Ravi Kumar, Wright, Kenneth Lee, Dodson, John Steven
• Primary Examiner(s): Anderson, Matthew
• Assistant Examiner(s): Li, Zhuo H.
• Application Number:
  US10/268,743
• Publication Number:
  US 20040073743A1
• Time in Patent Office: 971 Days
• Field of Search: 711 4- 5, 711/114, 711161-162, 711/200, 711/203, 711/209
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration

Abstract

A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the mapping engine maps Write memory requests addressed to the real address space currently associated with the reconfigured memory module to both the FROM and TO real address space. As will be appreciated, a memory module can be inserted, removed or replaced in physical memory without the operating system having to direct and control the reconfiguration of physical memory to accomplish the physical memory change.

Claims

1. A computing system coupled to a physical memory system having a plurality of memory modules for storing data as a plurality of memory blocks, each memory block comprising contiguous bytes of physical memory, and further coupled to at least one memory controller, wherein each memory controller of the at least one memory controller has one or more memory modules of the plurality of memory modules coupled thereto, and wherein each memory controller of the at least one memory controller responds to memory accesses by writing and reading memory blocks stored within one or more of the memory modules coupled thereto, the computing system comprising:

a processor device for generating memory accesses containing real addresses associated with memory locations of the physical memory system for reading and writing of data thereto;

a register within the processor device having a first field storing a first real address corresponding to a first memory module of the plurality of memory modules coupled thereto, wherein a first memory controller coupled to the first memory module is programmed to respond to memory requests addressed to the first real address, and a second field storing a second real address corresponding to a second memory module of the plurality of memory modules coupled thereto, wherein a second memory controller coupled to the second memory module is programmed to respond to memory requests addressed to the second real address;

a move engine within the processor device that, in response to a notification that a configuration of the first and second memory modules is being modified, copies the plurality of memory blocks from the first memory module to the second memory module based on the first real address and the second real address; and

a mapping engine within the processor device that issues a write memory request addressed to the first real address and the second real address in response to the processor device issuing a write memory request addressed to the real address stored in one of the first field or second field during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module, and that reprograms the second memory controller to respond to memory requests addressed to the first real address after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

2. The computing system of claim 1, wherein the mapping engine issues the write memory request addressed to both the first real address and second real address in response to the processor device requesting a write memory request addressed to the first real address during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

3. The computing system of claim 1, wherein the first memory module is removed from the physical memory system after the mapping engine enables the second memory controller to respond to memory accesses addressed to the first real address after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

4. The method of claim 3, wherein the first real address is within the current addressable space of the physical memory system prior to the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

5. The system of claim 1, wherein the second memory module is inserted into the physical memory system before the move engine copies the plurality of memory blocks from the first memory module to the second memory module.

6. The system of claim 5, wherein the first real address is outside the current addressable space of the physical memory system address prior to the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

7. A method of data processing within a data processing system, wherein the data processing system including a processor device for generating memory accesses containing physical addresses associated with memory locations of a physical memory system for reading and writing of data thereto, the physical memory system including a plurality of memory controllers, each responding to memory accesses requested by the processor device by writing and reading memory blocks stored within one or more memory modules coupled thereto, the method comprising:

setting a register in the processor device to indicate a first real address and a second real address corresponding to a first and a second memory module, respectively, the first and second memory modules being coupled to a first and a second memory controller, respectively;

copying the plurality of memory blocks from the first memory module to the second memory module based on the first real address and the second real address;

before completing the copying step, issuing a write memory request addressed to the first real address and the second real address in response to the processor device issuing a write memory request addressed to the real address stored in one of the first field or second field; and

after completing the copying step, configuring the first and second memory controllers to respond only to memory accesses addressed to the new real address.

8. The method of claim 7, wherein, during the copying step, a write memory request is issued that is addressed to the first real address and the second real address in response to the processor device issuing a write memory request addressed to the current real address.

9. The method of claim 7, further comprising the step of removing the first memory module from the physical memory system following the configuring step, and wherein the first real address is within a current addressable space for the physical memory system.

10. The method of claim 7, further comprising the step of inserting the first memory module into the memory system prior to the copying step, and wherein the second real address is outside a current addressable space for the physical memory.

11. The method of claim 7, the method further comprising notifying the processor that a configuration of the plurality of memory modules is being modified, and wherein the setting step is performed in response to the notification.

12. A data processing system comprising:

a physical memory system having a plurality of memory modules for storing data as a plurality of memory blocks, each memory block comprising contiguous bytes of physical memory;

a plurality of memory controllers, wherein each memory controller of the plurality of memory controllers has one or more memory modules of the plurality of memory modules coupled thereto, and wherein each memory controller of the plurality of memory controllers responds to memory accesses by writing and reading memory blocks stored within the one or more of the memory modules coupled thereto; and

a plurality of processor devices for generating memory accesses containing real addresses associated with memory locations of the physical memory system for reading and writing of data thereto, wherein each processor device of the plurality of processor devices includes;

a register having a first field storing a first real address corresponding to a first memory module of the plurality of memory modules coupled thereto, wherein a first memory controller coupled to the first memory module is programmed to respond to memory requests addressed to the first real address, and a second field storing a second real address corresponding to a second memory module of the plurality of memory modules coupled thereto, wherein a second memory controller coupled to the second memory module is programmed to respond to memory requests addressed to the second real address;

a move engine that, in response to a notification that a configuration of the first and second memory modules is being modified, copies the plurality of memory blocks from the first memory module to the second memory module based on the first real address and the second real address; and

a mapping engine that issues a write memory request addressed to the first real address and the second real address in response to the processor device requesting a write memory request addressed to the real address stored in one of the first field or second field during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module, and that reprograms the second memory controller to respond to memory requests addressed to the first real address after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

13. The system of claim 12, wherein the mapping engine issues the write memory request addressed to both the first real address and second real address in response to the processor device requesting a write memory request addressed to the first real address during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

14. The system of claim 12, wherein the first memory module is removed from the physical memory system after the mapping engine enables the second memory controller to respond to memory accesses addressed to the second real address after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

15. The method of claim 14, wherein the first real address is within the current addressable space of the physical memory system prior to the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

16. The system of claim 12, wherein the second memory module is inserted into the physical memory system before the move engine copies the plurality of memory blocks from the first memory module to the second memory module.

17. The system of claim 16, wherein the first real address is outside the current addressable space of the physical memory system address prior to the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.