Structure and method to fabricate ultra-thin Si channel devices

• US 6,905,941 B2
• Filed: 06/02/2003
• Issued: 06/14/2005
• Est. Priority Date: 06/02/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Kanarsky, Thomas S., Doris, Bruce B., Natzle, Wesley C., Ieong, Meikei
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US10/250,069
• Publication Number:
  US 20040241981A1
• Time in Patent Office: 743 Days
• Field of Search: 438/424, 438/425
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.

Claims

1. A method to fabricate ultra-thin Si channel devices comprising the steps of:

providing a structure having at least one trench region that includes a recessed, deposited oxide fill material, said at least one trench region is located in a nitride pad layer, a thermally grown oxide pad layer, a top-Si-containing layer of an SOI substrate and a portion of a buried insulating layer of said SOI substrate;

removing said nitride pad layer to expose said thermally grown oxide pad layer; and

removing said exposed thermally grown oxide pad layer and a portion of said recessed, deposited oxide fill material utilizing a chemical oxide removal process, said chemical oxide removal process etches the thermally grown oxide at a faster rate than the recessed, deposited oxide to provide a silicon-on-insulator structure having an oxide filled trench isolation region comprising said recessed, deposited oxide that has a height that is above an upper surface of said top Si-containing layer and a sloping oxide structure which has a tapered slope that extends outward from an upper surface of the recessed, deposited oxide to said upper surface of said top Si-containing layer, wherein no undercut regions are located beneath the top Si-containing layer.

2. The method of claim 1 wherein said recessed, deposited oxide fill material is formed by first depositing a deposited oxide layer atop the structure;

planarizing the deposited oxide layer to an upper surface of the pad nitride layer; and

recessing the planarized deposited oxide layer utilizing a timed etching process.

3. The method of claim 1 wherein said removing of said pad nitride layer is performed utilizing an etching step that selectively removes nitride as compared to oxide.

4. The method of claim 1 wherein said chemical oxide removal process is conducted in a gaseous mixture of HF and ammonia.

5. The method of claim 4 wherein said gaseous mixture of HF and ammonia is used in a ratio of HF to ammonia of from about 1:

10 to about 10;

1.

6. The method of claim 1 wherein said chemical oxide removal process is conducted at a pressure of about 30 mTorr or less and at temperature of about 25°

C.

7. The method of claim 1 further comprising forming a transistor on the top Si-containing layer abutting the oxide filled french isolation region.

8. A method to fabricate ultra-thin Si channel devices comprising the steps of:

providing a structure having at least one trench region that includes a recessed, deposited oxide fill material, said at least one trench region is located in a nitride pad layer, a thermally grown oxide pad layer, a top-Si-containing layer of an SOI substrate and a portion of a buried insulating layer of said SOI substrate;

removing said nitride pad layer to expose said thermally grown oxide pad layer; and

removing said exposed thermally grown oxide pad layer and a portion of said recessed, deposited oxide fill material utilizing a chemical oxide removal process, said chemical oxide removal process etches the thermally grown oxide at a faster rate than the recessed, deposited oxide to provide a silicon-on-insulator structure having an oxide filled trench isolation region comprising said recessed, deposited oxide that has a height that is below an upper surface of said top Si-containing layer and a sloping oxide structure, wherein no undercut regions are located beneath the top Si-containing layer.

9. The method of claim 8 wherein said recessed, deposited oxide fill material is formed by first depositing a deposited oxide layer atop the structure;

planarizing the deposited oxide layer to an upper surface of the pad nitride layer; and

recessing the planarized deposited oxide layer utilizing a timed etching process.

10. The method of claim 8 wherein said removing of said pad nitride layer is performed utilizing an etching step that selectively removes nitride as compared to oxide.

11. The method of claim 8 wherein said chemical oxide removal process is conducted in a gaseous mixture of HF and ammonia.

12. The method of claim 11 wherein said gaseous mixture of HF and ammonia is used in a ratio of HF to ammonia of from about 1:

10 to about 10;

1.

13. The method of claim 8 wherein said chemical oxide removal process is conducted at a pressure of about 30 mTorr or less and at temperature of about 25°

C.

14. The method of claim 8 further comprising forming a transistor on the top Si-containing layer abutting the oxide filled trench isolation region.