Photodetector circuit device and method thereof

• US 6,906,302 B2
• Filed: 07/30/2002
• Issued: 06/14/2005
• Est. Priority Date: 07/30/2002
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Drowley, Clifford I.
• Primary Examiner(s): Luu, Thanh X.
• Assistant Examiner(s): Sohn, Seung C.
• Application Number:
  US10/208,212
• Publication Number:
  US 20040021057A1
• Time in Patent Office: 1,050 Days
• Field of Search: 250/208.1, 250/559.26, 250/214.A, 356/5.01, 356/4.01, 348/308, 348/241, 257/290, 257/291, 257/292
• US Class Current: 250/208.1
• CPC Class Codes: G01S 17/36 with phase comparison between the received signal and the contemporaneously transmitted signal
• CPC Class Codes: G01S 7/4914 of detector arrays, e.g. charge-transfer gates
• CPC Class Codes: H01L 27/146 Imager structures

Abstract

A distance measuring device and photosensor circuit are disclosed herein. By pulsing a light source such as an LED to illuminate an object and measuring the phase difference between the light reflected from the object and the original phase of the light source, the distance to an object may be determined. In order to measure the phase difference, a CMOS photosensor or photosensor array may be used to receive the reflected light and store charge generated during different portions of time in different storage nodes or pixel cells. The difference between the amount of charge stored in different storage nodes can be used to determine the phase difference between the original light illuminating the object and the light reflected from the object. This phase difference can in turn be used to determine the distance to the object.

Claims

1. A circuit comprising:

a CMOS compatible photodetector to produce charge in response to incident light;

a plurality of storage nodes to store charge generated by said photodetector;

a plurality of control transistors to route charge from said photodetector to said plurality of storage nodes; and

a plurality of amplifiers coupled to said storage nodes, said plurality of amplifiers to provide an output related to an amount of charge stored in said storage nodes; and

a plurality of reset transistors coupled to said storage node, said plurality of reset transistors to precharge said storage nodes.

2. A circuit comprising:

a CMOS compatible photodetector to produce charge in response to incident light;

a plurality of storage nodes to store charge generated by said photodetector;

a plurality of control transistors to route charge from said photodetector to said plurality of storage nodes, wherein said plurality of control transistors include a first transfer transistor to route charge in response to a clock signal in-phase with a reference signal and a second transfer transistor to route charge in response to a clock signal out-of-phase with the reference signal; and

a plurality of amplifiers coupled to said storage nodes, said plurality of amplifiers to provide an output related to an amount of charge stored in said storage nodes.

3. The circuit as in claim 2, further including a shunt transistor coupled to said photodetector, said shunt transistor to provide blooming protection.

4. The circuit as in claim 2, further including a plurality of output transistors coupled to said plurality of amplifiers, said plurality of output transistors to switch the output of said plurality of amplifiers in response to a control signal.

5. The circuit as in claim 2, wherein said photodetector is a photodiode.

6. The circuit as in claim 5, wherein said photodiode is a pinned photodiode.

7. The circuit as in claim 2, wherein said photodetector is a photogate.

8. The circuit as in claim 2, wherein said control transistors are formed using a CMOS process.

9. A circuit comprising:

a CMOS compatible photodetector to produce charge in response to incident light;

a plurality of storage nodes to store charge generated by said photodetector;

a plurality of control transistors to route charge from said photodetector to said plurality of storage nodes;

a first reset transistor, said first reset transistor including;

a control node to be coupled to a first control signal;

a second current electrode to be coupled to a voltage supply; and

a first current electrode coupled to a first floating node;

a first buffer transistor, said first buffer transistor including;

a control node coupled to said first floating node;

a second current electrode to be coupled to said voltage supply; and

a first current electrode coupled to a current electrode of an output transistor;

said plurality of control transistors including a first transfer transistor, said first transfer transistor including;

a control node to be coupled to a second control signal;

a second current electrode coupled to said first floating node; and

a first current electrode coupled to a charge well of the photodetector;

a second reset transistor, said second reset transistor including;

a control node to be coupled to a third control signal;

a second current electrode to be coupled to a voltage supply; and

a first current electrode coupled to a second floating node;

a second buffer transistor, said second buffer transistor including;

a control node coupled to said second floating node;

a second current electrode to be coupled to said voltage supply; and

a first current electrode coupled to a current electrode of a second output transistor;

said plurality of control transistors further including a second transfer transistor, said second transfer transistor including;

a control node to be coupled to a fourth control signal;

a second current electrode coupled to said second floating node; and

a first current electrode coupled to said charge well of said photodetector;

wherein said photodetector includes the charge well coupled to said first current electrode of said first transfer transistor and further coupled to said first current electrode of said second transfer transistor.

10. The circuit as in claim 9, further including:

a third reset transistor, said third reset transistor including;

a control node to be coupled to a fifth control signal;

a second current electrode to be coupled to said voltage supply; and

a first current electrode coupled to a third floating node;

a third buffer transistor, said third buffer transistor including;

a control node coupled to said third floating node;

a second current electrode to be coupled to said voltage supply; and

a first current electrode coupled to a current electrode of a third output transistor;

a third transfer transistor, said third transfer transistor including;

a control node to be coupled to a sixth control signal;

a second current electrode coupled to said third floating node; and

a first current electrode coupled to a charge well of a photodetector;

a fourth reset transistor, said fourth reset transistor including;

a control node to be coupled to a third control signal;

a second current electrode to be coupled to a voltage supply; and

a first current electrode coupled to a second floating node;

a fourth buffer transistor, said fourth buffer transistor including;

a control node coupled to said second floating node;

a second current electrode to be coupled to said voltage supply; and

a first current electrode coupled to a current electrode of a second output transistor;

a fourth transfer transistor, said fourth transfer transistor including;

a control node to be coupled to a fourth control signal;

a second current electrode coupled to said second floating node; and

a first current electrode coupled to an input of said photodetector;

the photodetector, said photodetector including the charge well coupled to said first current electrode of said third transfer transistor and further coupled to said first current electrode of said fourth transfer transistor.

11. The circuit of claim 10, wherein the first floating node is a first storage node of the plurality of storage nodes, the second floating node is a second storage node of the plurality of storage nodes, the third floating node is a third storage node of the plurality of storage nodes, and the fourth floating node is a fourth storage node of the plurality of storage nodes.

12. The circuit of claim 9, wherein the first floating node is a first storage node of the plurality of storage nodes and the second floating node is a second storage node of the plurality of storage nodes.

13. A distance-measuring device comprising:

a light source;

a clock generator coupled to said light source; and

a photosensor, said photosensor including;

a CMOS compatible photodetector to produce charge in response to incident light;

a plurality of storage nodes to store charge generated by said photodetector;

a plurality of output transistors to couple said storage nodes to an output of said photodetector, said plurality of output transistors includes a plurality of amplifiers coupled to said storage nodes, said plurality of amplifiers to provide an output related to an amount of charge stored in said storage nodes;

a plurality of control transistors to selectively couple said photodetector to said storage nodes; and

a plurality of reset transistors coupled to said storage nodes, said plurality of reset transistors to precharge said storage nodes.

14. A distance-measuring device comprising:

a light source;

a clock generator coupled to said light source; and

a photosensor, said photosensor including;

a CMOS compatible photodetector to produce charge in response to incident light;

a plurality of storage nodes to store charge generated by said photodetector;

a plurality of output transistors to couple said storage nodes to an output of said photodetector, said plurality of output transistors includes a plurality of amplifiers coupled to said storage nodes, said plurality of amplifiers to provide an output related to an amount of charge stored in said storage nodes;

a plurality of control transistors to selectively couple said photodetector to said storage nodes, wherein said plurality of control transistors include a first transfer transistor to route charge in response to a clock signal in-phase with a reference signal and a second transfer transistor to route charge in response to a clock signal out-of-phase with the reference signal.

15. The distance-measuring device as in claim 14, wherein said photosensor further includes a shunt transistor coupled to said photodetector, said shunt transistor to provide blooming protection.

16. The distance-measuring device as in claim 14, wherein said output is indicative of a distance from said photosensor to an object.

17. The distance-measuring device as in claim 14, wherein said plurality of output transistors further includes transistors coupled to said plurality of amplifiers, said plurality of output transistors to switch the output of said plurality of amplifiers in response to a control signal.

18. The distance-measuring device as in claim 14, wherein said photodetector is a photodiode.

19. The distance-measuring device as in claim 18, wherein said photodiode is a pinned photodiode.

20. The distance-measuring device as in claim 14, wherein said photodetector is a photogate.

21. The distance-measuring device as in claim 14, wherein said control transistors are formed using a CMOS process.

22. The distance-measuring device as in claim 14, further including an array of photosensors.

23. A method comprising:

generating a reference clock;

pulsing a light source in synchronization with the reference clock;

illuminating a scene with the pulsing light source;

receiving light reflected from an object within the scene using a CMOS photosensor over a predetermined period of time; and

wherein receiving includes;

applying a clock in-phase with the reference clock to a first gate during a first portion of the predetermined period, such that charge generated by a photodetector is stored in a first storage node;

applying a clock out-of-phase with the reference clock to a second gate during a second portion of the predetermined period, such that charge generated by the photodetector is stored in a second storage node; and

determining a distance to the object based on an amount of charge stored in the first storage node and an amount of charge stored in the second storage node.

24. The method as in claim 23, wherein the out-of-phase clock is 180 degrees out-of-phase with the reference signal.

25. The method as in claim 23, wherein the out-of-phase clock is between 90 degrees out-of-phase and 180 degrees out-of-phase, inclusive.

26. A method comprising:

generating a reference clock having a first frequency during a first portion of a phase detection cycle and having a second frequency, different from the first frequency, during a second portion of the phase detection cycle;

pulsing a light source in synchronization with the reference clock during the first portion of the phase detection cycle;

illuminating a scene with the pulsing light source;

receiving light reflected from an object within the scene using a CMOS photosensor over a first predetermined period of time, wherein receiving includes;

applying a clock in-phase with the reference clock to a first gate during a first portion of the first predetermined period, such that charge generated by a photodetector is stored in a first storage node;

applying a clock out-of-phase with the reference clock to a second gate during a second portion of the first predetermined period, such that charge generated by the photodetector is stored in a second storage node;

determining a first phase difference based on an amount of charge stored in the first storage node and an amount of charge stored in the second storage node;

pulsing the light source in synchronization with the reference clock during the second portion of the phase detection cycle;

illuminating the scene with the pulsing light source;

receiving light reflected from the object within the scene using the CMOS photosensor over a second predetermined period of time, wherein receiving includes;

applying a clock in-phase with the reference clock to the first gate during a first portion of the second predetermined period, wherein charge generated by the CMOS photosensor is stored the first storage node;

applying a clock out-of-phase with the reference clock to a second gate during a second portion of the second predetermined period, wherein charge generated by the photodetector is stored in the second storage node;

determining a second phase difference based on an amount of charge stored in the first storage node and an amount of charge stored in the second storage node; and

determining a distance to the object based on the first phase difference and the second phase difference.

27. The method as in claim 26, further includes determining a distance based on additional phase differences and addition clock frequencies.