Method of isolating the current sense on power devices while maintaining a continuous stripe cell

• US 6,906,362 B2
• Filed: 12/10/2002
• Issued: 06/14/2005
• Est. Priority Date: 01/22/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Reichl, Dwayne S., Lange, Douglas J.
• Primary Examiner(s): Blum, David S.
• Application Number:
  US10/315,719
• Publication Number:
  US 20030141522A1
• Time in Patent Office: 917 Days
• Field of Search: 257/262
• US Class Current: 257/262
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

Claims

1. An integrated circuit, comprising:

a die;

an active area disposed on said die, said active area including source dopants and contacts, an active area metal layer overlying said active area;

a sense area disposed on said die, a sense area metal layer overlying said sense area;

a plurality of spaced-apart polysilicon gate stripes and body stripes disposed on said die, said plurality of polysilicon gate stripes and body stripes extending in a continuous and uninterrupted manner from said active area into said sense area;

a first region surrounding a periphery of said sense area, said first region having excluded therefrom source dopants and contacts;

an etched region disposed over said first region, said etched region separating and electrically isolating said sense area metal layer from said active area metal layer.

2. The integrated circuit of claim 1, wherein said integrated circuit is a transistor.

3. The integrated circuit of claim 2, wherein said transistor is one of an integrated gate bipolar transistor and a metal oxide field effect transistor.

4. The integrated circuit of claim 2, wherein said transistor is a trench stripe device.

5. The integrated circuit of claim 1, further comprising a control circuit integral and monolithic with said die and configured for being electrically connected to said sense area.

6. The integrated circuit of claim 1, wherein said sense area comprises a source exclude region from which source dopants have been excluded.

7. The integrated circuit of claim 6, wherein said sense area further comprises a source region, said source region doped with source dopants.

8. The integrated circuit of claim 7, wherein said source region surrounds said source exclude region, said first region surrounding said source region.