Semiconductor device with vertical transistor formed in a silicon-on-insulator substrate

• US 6,906,372 B2
• Filed: 11/27/2001
• Issued: 06/14/2005
• Est. Priority Date: 12/06/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kajiyama, Takeshi, Yamada, Takashi
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Lewis, Monica
• Application Number:
  US09/993,967
• Publication Number:
  US 20020076880A1
• Time in Patent Office: 1,295 Days
• Field of Search: 257/68, 257/71, 257296-313, 257905-908, 438/296
• US Class Current: 257/301
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/395 the transistor being vertical
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A semiconductor device has an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween. A groove is formed in the element substrate with a depth extending from a top surface of the semiconductor layer into the dielectric film, the groove having a width-increased groove portion in the dielectric film as to expose a bottom surface of the semiconductor layer. An impurity diffusion source is buried in the width-increased groove portion to be contacted with the bottom surface. A transistor is formed to have a first diffusion layer being formed through impurity diffusion from the impurity diffusion source to the bottom surface of the semiconductor layer, a second diffusion layer formed through impurity diffusion to the top surface of the semiconductor layer, and a gate electrode formed at a side face of the groove over the impurity diffusion source with a gate insulation film between the side face and the gate electrode.

Claims

1. A semiconductor device comprising:

an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate;

said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer;

an impurity diffusion source buried in said laterally receded portion of said groove to be contacted with said portion of the bottom surface of said semiconductor layer;

a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said top surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode; and

a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove, for constitution of a DRAM cell together with said transistor,

wherein said groove is formed deep enough to reach the inside of said semiconductor substrate after penetration through said dielectric film,

wherein a buried strap for use as said impurity diffusion source is formed and buried in said laterally receded portion overlying said storage electrode to be contacted with said semiconductor layer only at the bottom surface thereof,

wherein said buried strap is covered with a cap insulation film with the gate electrode of said transistor embedded to overlie said cap insulation film, and

wherein said buried strap comprises a first strap buried on said storage electrode and a second strap stacked on the first strap and buried in said laterally receded portion being in contact with said semiconductor layer only at the bottom surface thereof.

9. The semiconductor device according to claim 1, wherein said element substrate is a silicon-on-insulator substrate.

2. A semiconductor device comprising:

an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate;

said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer;

an impurity diffusion source buried in said laterally receded portion of said groove to be contacted with said portion of the bottom surface of said semiconductor layer;

a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said top surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode; and

a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove, for constitution of a DRAM cell together with said transistor,

wherein said groove is formed deep enough to reach the inside of said semiconductor substrate after penetration through said dielectric film,

wherein a buried strap for use as said impurity diffusion source is formed and buried in said laterally receded portion overlying said storage electrode to be contacted with said semiconductor layer only at the bottom surface thereof,

wherein said buried strap is covered with a cap insulation film with the sate electrode of said transistor embedded to overlie said cap insulation film, and

wherein said laterally receded portion of said groove is formed to cover an entire range of a thickness of said dielectric film whereas the storage electrode of said capacitor is half buried in said laterally receded portion with said buried strap being embedded on said storage electrode to be contacted with said semiconductor layer only at the bottom surface thereof.

3. A semiconductor device comprising:

an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate;

said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer;

an impurity diffusion source buried in said laterally receded portion of said groove to be contacted with said portion of the bottom surface of said semiconductor layer;

a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said to surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode; and

a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove, for constitution of a DRAM cell together with said transistor,

wherein said groove is formed deep enough to reach the inside of said semiconductor substrate after penetration through said dielectric film,

wherein said semiconductor layer is partitioned into a plurality of element regions by an element isolating insulative film formed and buried deep enough to reach said dielectric film while letting two DRAM cells be disposed at opposite end portions of each said element region to thereby constitute a DRAM cell array with a word line connected to the gate electrode of said transistor and a bit line coupled to the second diffusion layer of said transistor said word line and said bit line being continuously disposed to cross each other, and

wherein said bit line is in contact with said second diffusion layer of each DRAM cell at a position adjacent to word lines at both ends of each said element region, and wherein a body wire lead is formed to be contacted with said semiconductor layer across central part of said element region for applying a fixed potential to said semiconductor layer.

4. A semiconductor device comprising:

an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate;

said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer;

an impurity diffusion source buried in said laterally receded portion of said groove to be contacted with said portion of the bottom surface of said semiconductor layer;

a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said top surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode; and

a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove, for constitution of a DRAM cell together with said transistor,

wherein said groove is formed deep enough to reach the inside of said semiconductor substrate after penetration through said dielectric film, and

wherein said semiconductor layer is partitioned into a plurality of element regions by an element isolating insulative film formed and buried with a depth failing to reach said dielectric film while letting two DRAM cells be disposed at opposite end portions of each said element region to thereby constitute a DRAM cell array with a word line connected to the gate electrode of said transistor and a bit line coupled to the second diffusion layer of said transistor said word line and said bit line being continuously disposed to cross each other.

5. A semiconductor device comprising:

an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate;

said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into the inside of said semiconductor substrate after penetration through said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer;

a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove;

an impurity diffusion source buried in said laterally receded portion of said groove to serve as a buried strap, bottom surface and top surface of said impurity diffusion source being contacted with said storage electrode and said portion of the bottom surface of said semiconductor layer, respectively;

a cap insulation film formed in said groove to cover said impurity diffusion source; and

a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said top surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode, said transistor constituting a DRAM cell with said trench capacitor,

wherein said buried strap comprises a first strap buried on said storage electrode and a second strap stacked on the first strap and buried in said increased width portion being in contact with said semiconductor layer only at the bottom surface thereof.

6. A semiconductor device comprising:

an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate;

said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into the inside of said semiconductor substrate after penetration through said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer;

a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove;

an impurity diffusion source buried in said laterally receded portion of said groove to serve as a buried strap, bottom surface and top surface of said impurity diffusion source being contacted with said storage electrode and said portion of the bottom surface of said semiconductor layer, respectively;

a cap insulation film formed in said groove to cover said impurity diffusion source; and

a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said to surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode, said transistor constituting a DRAM cell with said trench capacitor,

wherein said laterally receded groove portion of said groove is formed to cover an entire range of a thickness of said dielectric film whereas the storage electrode of said capacitor as half buried in said increased width groove portion with said buried strap being embedded on said storage electrode to be contacted with said semiconductor layer only at the bottom surface thereof.

7. A semiconductor device comprising:

an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate;

said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into the inside of said semiconductor substrate after penetration through said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer;

a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove;

an impurity diffusion source buried in said laterally receded portion of said groove to serve as a buried strap, bottom surface and top surface of said impurity diffusion source being contacted with said storage electrode and said portion of the bottom surface of said semiconductor layer, respectively;

a cap insulation film formed in said groove to cover said impurity diffusion source; and

a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said top surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode, said transistor constituting a DRAM cell with said trench capacitor,

wherein said semiconductor layer is partitioned into a plurality of element regions by an element isolating insulative film as formed and buried deep enough to reach said dielectric film while letting two DRAM cells be disposed at opposite end portions of each said element region to thereby constitute a DRAM cell array with a word line connected to the gate electrode of said transistor and a bit line coupled to said second diffusion layer of said transistor, said word line and bit line being continuously disposed to cross each other, and

wherein said bit line is in contact with said second diffusion layer of each DRAM cell at a position adjacent to word lines at both ends of each said element region, and wherein a body wire lead is formed to be contacted with said semiconductor layer across central part of said element region for applying a fixed potential to said semiconductor layer.

8. A semiconductor device comprising:

an element substrate including a semiconductor layer of a first conductivity type being formed over a semiconductor substrate with a dielectric film interposed therebetween and such that said dielectric film is in contact with said semiconductor substrate;

said element substrate having a groove formed therein with a depth extending from a top surface of said semiconductor layer into the inside of said semiconductor substrate after penetration through said dielectric film, said groove in said dielectric film being receded laterally so as to expose a portion of a bottom surface of said semiconductor layer and such that the width of said groove in said dielectric film is greater than that of said groove in said semiconductor layer;

a trench capacitor formed under said dielectric film to have a storage electrode as half buried in said groove;

an impurity diffusion source buried in said laterally receded portion of said groove to serve as a buried strap, bottom surface and top surface of said impurity diffusion source being contacted with said storage electrode and said portion of the bottom surface of said semiconductor layer, respectively;

a cap insulation film formed in said groove to cover said impurity diffusion source; and

a transistor having a first diffusion layer of a second conductivity type being formed through impurity diffusion from said impurity diffusion source to said bottom surface of said semiconductor layer, a second diffusion layer of the second conductivity type formed through impurity diffusion to said top surface of said semiconductor layer, and a gate electrode formed at a side face of said groove over said impurity diffusion source with a gate insulation film between said side face and said gate electrode, said transistor constituting a DRAM cell with said trench capacitor,

wherein said semiconductor layer is partitioned into a plurality of element regions by an element isolating insulative film as formed and buried with a depth failing to reach said dielectric film while letting two DRAM cells be disposed at opposite end portions of each said element region to thereby constitute a DRAM cell array with a word line connected to the gate electrode of said transistor and a bit line coupled to said second diffusion layer of said transistor, said word line and bit line being continuously disposed to cross each other.