Semiconductor chip with gate dielectrics for high-performance and low-leakage applications

• US 6,906,398 B2
• Filed: 01/02/2003
• Issued: 06/14/2005
• Est. Priority Date: 01/02/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Yang, Fu-Liang, Hu, Chenming
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US10/335,962
• Publication Number:
  US 20040129995A1
• Time in Patent Office: 894 Days
• Field of Search: 257/297, 257/300, 257/310, 257/316, 257/500
• US Class Current: 257/500
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

Both high performance and low leakage current devices can be formed on a single wafer without significant additional processing steps by the formation of an ultra-thin gate dielectric and a high-permittivity gate dielectric, respectively, in regions wherein switching speed and low leakage current, respectively, are desired. Logic and embedded memory regions can be performance optimized on the same integrated circuit.

Claims

1. An integrated circuit comprising:

a substrate;

a first transistor having a first gate dielectric with a first oxide equivalent thickness, comprising an ultra-thin gate dielectric formed on the substrate; and

a second transistor having a second gate dielectric with a second oxide equivalent thickness, comprising a high-permittivity dielectric material formed on the substrate, wherein the second oxide equivalent thickness is different than the first oxide equivalent thickness.

2. The integrated circuit of claim 1 wherein said substrate is selected from the group consisting of silicon, germanium, and silicon-on-insulator.

3. The integrated circuit of claim 1 wherein said ultra-thin gate dielectric is selected from the group consisting of silicon oxide, silicon oxynitride, and silicon nitride.

4. The integrated circuit of claim 1 wherein said high-permittivity dielectric material is selected from the group consisting of metallic oxides, oxynitrides of metals, metallic silicates, and metallic aluminates.

5. The semiconductor chip of claim 1 wherein the relative permittivity of said high-permittivity dielectric layer is greater than 8.

6. The semiconductor chip of claim 1 wherein said high-permittivity dielectric material is from 2 to 500 angstroms thick.

7. The semiconductor chip of claim 1 wherein said ultra-thin gate dielectric has an equivalent silicon oxide thickness of less than 10 Angstroms.

8. The semiconductor chip of claim 1 further comprising an interfacial layer underlying said high-permittivity dielectric material.

9. The semiconductor chip of claim 8 wherein said interfacial layer is selected from the group consisting of silicon oxide, silicon oxynitride, metallic silicates, and metallic aluminates.

10. An integrated circuit comprising:

a substrate;

a first region formed on the substrate, the first region having formed therein a plurality of first transistors, each of said plurality of first transistors including;

a first source region;

a first drain region;

a first channel region formed between the first source and first drain regions; and

a first gate electrode electrically separated from the first channel region by a first gate dielectric having a first oxide equivalent thickness, comprising a high permittivity dielectric material; and

a second region formed on the substrate, the second region having formed therein a plurality of first transistors, each of said plurality of second transistors including;

a second source region;

a second drain region;

a second channel region formed between the second source and second drain regions; and

a second gate electrode electrically separated from the second channel region by a second gate dielectric having a second oxide equivalent thickness, comprising an ultra-thin dielectric material, wherein the second oxide equivalent thickness is different than the first oxide equivalent thickness.

11. The integrated circuit of claim 10 wherein the ultra-thin dielectric material has an equivalent silicon oxide thickness of less than 10 angstroms.

12. The integrated circuit of claim 10 wherein the first region is separated from the second region by an isolation structure selected from the group consisting of shallow trench isolation, localized oxidation of silicon (LOCOS), and silicon islands formed on a silicon-on-insulator (SOI) substrate.

13. The integrated circuit of claim 10 wherein the high-permittivity dielectric material is selected from the group consisting of metallic oxides, oxynitrides of metals, metallic silicates, and metallic aluminates.

14. The integrated circuit of claim 10 wherein the high-permittivity dielectric material has a relative permittivity of at least 8.

15. The integrated circuit of claim 10 wherein the first region is a memory array.

16. The integrated circuit of claim 10 further including an interfacial layer between the substrate and the high-permittivity dielectric material.

17. The integrated circuit of claim 10 wherein the ultra-thin dielectric material is selected from the group consisting of silicon oxide, silicon oxynitride, and silicon nitride.