Multiple dice package

• US 6,906,406 B2
• Filed: 12/19/2002
• Issued: 06/14/2005
• Est. Priority Date: 12/19/2002
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kuo, Shun Meen, Drye, James E., Hwang, Lih-Tyng
• Primary Examiner(s): Andujar, Leonardo
• Application Number:
  US10/324,533
• Publication Number:
  US 20040119150A1
• Time in Patent Office: 908 Days
• Field of Search: 257684-686, 257701-703
• US Class Current: 257/685
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/854 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor device for multiple dice is provided that reduces insertion loss and return loss. In an example embodiment, the semiconductor device comprises: a package 20 comprising a mount surface 14 to which dice 61 and 65 are mounted, and a bond pad surface 25 defining at least a first die area 27 and a second die area 29, wherein the second die area 29 is different in form from the first die area 27.

Claims

1. A package for multiple semiconductor dice, the package comprising:

a die mount surface;

a bond pad surface residing over the die mount surface,

wherein the bond pad surface includes a cavity having

a first portion defining a first generally rectangular die receiving area and

a second portion defining a second generally rectangular die receiving area, and

wherein the first and the second die receiving areas have differing dimensions;

a first semiconductor die mounted to the die mount surface in the first generally rectangular die receiving area and a second semiconductor die mounted to the die mount surface in the second generally rectangular die receiving area;

a first set of package bond pads on the bond pad surface proximate to the first portion of the cavity; and

a second set of package bond pads on the bond pad surface proximate to the second portion of the cavity, wherein each of the second set of package bond pads is implemented in an electrical pathway electrically coupled to a bond pad of the second semiconductor die, wherein each package bond pad of the second set has an impedance sized for controlling the impedance of the electrical pathway in which it is implemented;

a third semiconductor die located in the first generally rectangular die receiving area;

wherein the third semiconductor die is mounted to the die mount surface.

2. A package as in claim 1 wherein at least one of the first set of package bond pads on the bond pad surface has an impedance different from the impedance of at least one of the second set of package bond pads on the bond pad surface.

3. A package as in claim 1 wherein at least one of the first set of package bond pads on the bond pad surface has an impedance different from the impedance of another of the first set of package bond pads on the bond pad surface.

4. A package as in claim 1 wherein at least one of the second set of package bond pads on the bond pad surface has an impedance different from the impedance of another of the second set of package bond pads on the bond pad surface.

5. A package as in claim 1 wherein the second semiconductor die is less than about 50 microns from the bond surface.

6. A package as in claim 5 wherein the second semiconductor die is more than about 20 microns from the bond surface.

7. A package as in claim 1 further comprising a wire bond between a die bond pad on the second semiconductor die and a package bond pad, wherein the wire bond is less than about 2 millimeters in length.

8. A package as in claim 7 wherein the wire bond is less than about 1 millimeter in length.

9. A package as in claim 1 wherein the first semiconductor die comprises a control device and the second semiconductor die comprises a RF device.

10. A package as in claim 9 wherein the RF device comprises a MEMS device.