Semiconductor device assemblies and packages including multiple semiconductor devices and methods

• US 6,906,415 B2
• Filed: 06/27/2002
• Issued: 06/14/2005
• Est. Priority Date: 06/27/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jiang, Tongbi, Chye, Lim Thiam, Yean, Tay Wuu, Fee, Setho Sing
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Dao H.
• Application Number:
  US10/184,340
• Publication Number:
  US 20030230801A1
• Time in Patent Office: 1,083 Days
• Field of Search: 257/668, 257/676, 257/723, 257/685, 257/724, 257/790, 257/686, 257/777, 257/781, 438/126, 438/108, 438/109
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85424 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1064 : Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/045 : Hierarchy auxiliary PCB, i.e. more than two levels of hierarchy for daughter PCBs are important
• CPC Class Codes: H05K 2201/049 : PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/09181 : Notches in edge pads
• CPC Class Codes: H05K 2201/10727 : Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3442 : having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Claims

1. A semiconductor device assembly, comprising:

an interposer including at least one receptacle formed therein;

at least one semiconductor device positioned at least partially within the at least one receptacle, a backside of the at least one semiconductor device being substantially coplanar with a surface of the interposer or located within a plane which extends through the interposer;

at least one intermediate conductive element extending from a bond pad of the at least one semiconductor device to a bond pad of the interposer, the at least one intermediate conductive element being bonded to at least the bond pad of the interposer; and

at least another semiconductor device at least partially superimposed over a bond pad-bearing surface of the at least one semiconductor device and at least partially supported by the interposer.

2. The semiconductor device assembly of claim 1, wherein the at least one receptacle extends substantially through the interposer.

3. The semiconductor device assembly of claim 1, wherein the at least one semiconductor device is completely laterally surrounded by the interposer.

4. The semiconductor device assembly of claim 1, wherein active surfaces of the at least one semiconductor device and the at least another semiconductor device face in substantially the same direction.

5. The semiconductor device assembly of claim 4, further comprising:

at least one intermediate conductive element extending laterally between and electrically connecting a bond pad of the at least one semiconductor device to a corresponding contact area of the interposer; and

at least another intermediate conductive element extending laterally between and electrically connecting a bond pad of the at least another semiconductor device and another corresponding contact area of the interposer.

6. The semiconductor device assembly of claim 5, wherein the corresponding contact area and the another corresponding contact area are located on the same surface of the interposer.

7. The semiconductor device assembly of claim 4, wherein the at least another semiconductor device includes at least one redistribution circuit on a surface thereof.

8. The semiconductor device assembly of claim 7, further comprising:

at least one discrete conductive element electrically connecting a bond pad of the at least one semiconductor device and a portion of the at least one redistribution circuit in alignment with the bond pad, and

at least another discrete conductive element electrically connecting another portion of the at least one redistribution circuit and a corresponding contact area of the interposer in alignment with the another portion.

9. The semiconductor device assembly of claim 8, wherein the at least one redistribution circuit is carried upon a back side of the at least another semiconductor device.

10. The semiconductor device assembly of claim 9, further comprising:

at least one intermediate conductive element extending laterally between and electrically connecting a bond pad on said active surface of the at least another semiconductor device and another corresponding contact area of said interposer.

11. The semiconductor device assembly of claim 8, wherein the at least one redistribution circuit is carried upon said active surface of the at least another semiconductor device.

12. The semiconductor device assembly of claim 11, further comprising:

at least another discrete conductive element electrically connecting a bond pad on the active surface of said at least another semiconductor device and another corresponding contact area of the interposer in substantial alignment with said bond pad.

13. The semiconductor device assembly of claim 1, wherein active surfaces of the at least one semiconductor device and the at least another semiconductor device face one another.

14. The semiconductor device assembly of claim 13, further comprising:

at least one discrete conductive element extending between and electrically connecting a bond pad of the at least one semiconductor device and a corresponding bond pad of the at least another semiconductor device in substantially alignment with the bond pad; and

at least another discrete conductive element extending between and electrically connecting another bond pad of the at least another semiconductor device and a corresponding contact area of the interposer in substantial alignment with the another bond pad.

15. The semiconductor device assembly of claim 14, wherein the corresponding bond pad of said at least another semiconductor device comprises a portion of a redistribution circuit on the active surface of the at least another semiconductor device.

16. The semiconductor device assembly of claim 15, wherein the redistribution circuit further comprises a circuit trace in communication with the corresponding bond pad and a redistribution bond pad at an opposite end of the circuit trace.

17. The semiconductor device assembly of claim 16, wherein the another bond pad of the at least another semiconductor device comprises the redistribution bond pad.

18. The semiconductor device assembly of claim 13, comprising at least two semiconductor devices positioned at least partially within the at least one receptacle.

19. The semiconductor device assembly of claim 18, wherein back sides of the at least two semiconductor devices face one another.

20. The semiconductor device assembly of claim 19, wherein another semiconductor device is positioned adjacent to an active surface of each of the at least two semiconductor devices.

21. The semiconductor device assembly of claim 1, wherein:

circuitry of the at least another semiconductor device is in electrical communication with corresponding circuitry of the interposer; and

circuitry of the at least one semiconductor device is in electrical communication with corresponding circuitry of at least one of the at least another semiconductor device and the interposer.

22. The semiconductor device assembly of claim 21, further comprising:

a quantity of underfill material between at least peripheral edges of the at least one semiconductor device and surfaces of the at least one receptacle.

23. The semiconductor device assembly of claim 22, wherein the underfill material is located between adjacent surfaces of the at least one semiconductor device and the at least another semiconductor device.

24. The semiconductor device assembly of claim 21, further comprising:

encapsulant material covering at least a peripheral edge of the at least another semiconductor device and adjacent regions of the interposer.

25. The semiconductor device assembly of claim 21, further comprising:

conductive structures on the interposer for electrical connection of the interposer to a higher-level substrate.

26. The semiconductor device assembly of claim 25, wherein the conductive structures comprise contact pads on a surface of the interposer and discrete conductive elements that protrude from the surface of the interposer.

27. The semiconductor device assembly of claim 26, wherein the discrete conductive elements protrude from an opposite surface from that by which the at least another semiconductor device is at least partially supported.

28. The semiconductor device assembly of claim 26, wherein the discrete conductive elements protrude from the same surface as that by which the at least another semiconductor device is at least partially supported.

29. The semiconductor device assembly of claim 26, wherein the discrete conductive elements comprise at least one of balls, bumps, columns, pillars, and pins of conductive material.

30. The semiconductor device assembly of claim 1, wherein the interposer includes:

first contact pads on a first surface thereof for establishing electrical communication between circuitry of the interposer or a semiconductor device supported thereby and a higher-level substrate; and

second contact pads on a second surface thereof, opposite the first surface, for establishing electrical communication between the circuitry of the interposer or the semiconductor device supported thereby and another semiconductor device assembly at least partially superimposed over the interposer.

31. A semiconductor device assembly, comprising:

an interposer including a first surface, a second surface opposite the first surface, and at least one receptacle extending from the first surface to the second surface;

a first semiconductor device positioned at least partially over the first surface and including an active surface, at least a portion of the active surfaca facing the at least one receptacle;

at least one first discrete conductive element electrically connecting a bond pad of the first semiconductor device and a corresponding contact pad at the first surface of the interposer that is in substantial alignment with the bond pad;

a second semiconductor device positioned at least partially over to the second surface and including an active surface, at least a portion of which faces the at least one receptacle; and

at least one second discrete conductive element electrically connecting a bond pad of the second semiconductor device and a corresponding bond pad of the first semiconductor device through the at least one receptacle.

32. The semiconductor device assembly of claim 31, wherein the at least one second discrete conductive element comprises at least one of a ball, bump, column, pillar, and pin.

33. The semiconductor device assembly of claim 31, wherein the corresponding bond pad comprises a portion of a redistribution circuit on the active surface of the first semiconductor device.

34. The semiconductor device assembly of claim 33, wherein the redistribution circuit further comprises a conductive trace in electrical communication with the corresponding bond pad and a redistribution bond pad at an end of the conductive trace opposite from the corresponding bond pad.

35. The semiconductor device assembly of claim 34, wherein the redistribution bond pad is positioned adjacent to an outer periphery of the second semiconductor device.

36. A multidie semiconductor device package, comprising:

an interposer, comprising;

a substrate with first and second surfaces;

a receptacle extending between the first and second surfaces; and

bond pad carried by at least the first surface;

at least one first-level semiconductor device positioned within the receptacle, a backside of the at least one first-level semiconductor device being substantially coplanar with the second surface of the interposer or located between the first and second surfaces of the interposer, each first-level semiconductor device also having an active surface;

a second-level semiconductor device positioned over the first surface of the interposer and attached thereto, the second-level semiconductor device having an active surface;

at least one intermediate conductive element extending at least partially laterally between a bond pad of the at least one first-level semiconductor device and a corresponding bond pad carried by the first surface of the substrate of the interposer, the at least one intermediate conductive element being bonded to at least the corresponding bond pad; and

electrical connections connecting the second-level semiconductor device to corresponding bond pads of the interposer.

37. The multidie semiconductor device package of claim 36, further comprising outer connectors for attaching the multidie semiconductor device package to conductors on an object.

38. The multidie semiconductor device package of claim 37, wherein the outer connectors are mounted on the second surface of the substrate and conductively connected to the electrical connections.

39. The multidie semiconductor device package of claim 38, wherein the outer connectors are conductively connected to the electrical connections by conductive vias extending between the first surface and the second surface of the substrate.

40. The multidie semiconductor device package of claim 37, wherein the object comprises one of a circuit board and another semiconductor device package.

41. The multidie semiconductor device package of claim 37, wherein the outer connectors comprise one of conductive balls, conductive bumps, conductive columns, conductive pins and plug-in type electrical connectors.

42. The multidie semiconductor device package of claim 36, wherein the second-level semiconductor device has a larger footprint than that of the at least one first-level semiconductor device.

43. The multidie semiconductor device package of claim 36, wherein the second-level semiconductor device is larger than the receptacle in at least one of an X and Y dimension.

44. The multidie semiconductor device package of claim 36, further comprising:

elongate, intermediate conductive elements connecting bond pads of the at least one first-level semiconductor device to corresponding bond pads of the interposer.

45. The multidie semiconductor device package of claim 36, wherein the electrical connections connecting the second-level semiconductor device to the corresponding bond pads comprise elongate, intermediate conductive elements.

46. The multidie semiconductor device package of claim 36, wherein the electrical connections connecting the second-level semiconductor device to the corresponding bond pads comprise discrete conductive elements interposed between the active surface of the second-level semiconductor device and the corresponding bond pads.

47. The multidie semiconductor device package of claim 46, wherein the electrical connections connecting the second-level semiconductor device to the corresponding bond pads comprise one of conductive balls, conductive bumps, conductive pins, conductive columns, conductive pillars, and conductive regions of z-axis-conductive or conductor-filled elastomer.

48. The multidie semiconductor device package of claim 46, wherein bond pads of the at least one first-level semiconductor device are connected to corresponding bond pads on the active surface of the second-level semiconductor device by first-level electrical connections.

49. The multidie semiconductor device package of claim 48, wherein the first-level electrical connections between the bond pads of the at least one first-level semiconductor device and the corresponding bond pads of the second-level semiconductor device comprise one of conductive balls, conductive bumps, conductive pins, conductive columns, conductive pillars and conductive regions of z-axis-conductive or conductor-filled elastomer.

50. The multidie semiconductor device package of claim 46, wherein the second-level semiconductor device is attached to the first surface of the substrate of the interposer.

51. The multidie semiconductor device package of claim 36, wherein a back side of the at least one first-level semiconductor device is substantially coplanar with the second surface of the substrate.

52. The multidie semiconductor device package of claim 36, further comprising a third-level semiconductor device with an active surface, bond pads on the active surface of the third-level semiconductor device being attached by conductive connectors to the second surface of the substrate.

53. The multidie semiconductor device package of claim 52, wherein the conductive connectors on the third-level semiconductor device comprise one of conductive balls, conductive bumps, conductive pins, conductive columns, conductive pillars, conductive regions of z-axis-conductive or conductor-filled elastomer, bond wires, conductive tape-automated bonding elements, and leads.

54. The multidie semiconductor device package of claim 52, further comprising a second first-level semiconductor device positioned below the at least one first-level semiconductor device in the receptacle, the second first-level semiconductor device electrically attached to the third-level semiconductor device in a flip-chip arrangement.

55. The multidie semiconductor device package of claim 36, wherein the at least one first-level semiconductor device comprises a plurality of first-level semiconductor devices mounted side-by-side in the receptacle.