High-speed domino logic with improved cascode keeper

• US 6,906,556 B2
• Filed: 06/30/2003
• Issued: 06/14/2005
• Est. Priority Date: 06/30/2003
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Choe, Swee Yew
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/611,134
• Publication Number:
  US 20040263209A1
• Time in Patent Office: 715 Days
• Field of Search: 326 95- 98
• US Class Current: 326/95
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A high-speed domino logic with improved cascode keeper circuit uses an inverter delay element and an additional transistor to introduce a transition delay time and node isolation time to avoid the contest or “fight” between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of high-speed domino logic with improved cascode keeper circuit. The high-speed domino logic with improved cascode keeper circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only a minimum of one new inverter and one new are required, the modification of the invention is space efficient and readily incorporated into existing designs.

Claims

1. A high-speed domino logic with improved cascode keeper circuit comprising:

a first supply voltage;

a second supply voltage;

a first clock signal;

a high-speed domino logic with improved cascode keeper OUT terminal;

an inverted and delayed first clock signal being approximately 180 degrees out of phase with said first clock signal and delayed with respect to said first clock signal by a predetermined time;

a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode, said first clock signal being coupled to said first transistor control electrode, said first transistor second flow electrode being coupled to a first node, said first transistor having a first threshold voltage;

a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said second transistor second flow electrode being coupled to said first node, said second transistor control electrode being coupled to said high-speed domino logic with improved cascode keeper OUT terminal, said second transistor having substantially said first threshold voltage;

a logic block, said logic block comprising at least one logic block input terminal and a logic block output terminal;

a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said third transistor first flow electrode being coupled to said logic block output terminal, said third transistor second flow electrode being coupled to said second supply voltage, said third transistor control electrode being coupled to said first clock signal;

a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said first supply voltage being coupled to said fourth transistor first flow electrode, said fourth transistor second flow electrode being coupled to second transistor first flow electrode, said fourth transistor control electrode being coupled to said inverted and delayed first clock signal;

an inverter, said inverter comprising an inverter input terminal and an inverter output terminal, said inverter input terminal being coupled to said first node, said inverter output terminal being coupled to said OUT terminal of said high-speed domino logic with improved cascode keeper circuit.

2. The high-speed domino logic with improved cascode keeper circuit of claim 1, wherein;

said logic block of said high-speed domino logic with improved cascode keeper circuit comprises logic gates.

3. The high-speed domino logic with improved cascode keeper circuit of claim 2, wherein;

said logic block of said high-speed domino logic with improved cascode keeper circuit comprises an AND gate.

4. The high-speed domino logic with improved cascode keeper circuit of claim 2, wherein;

said logic block of said high-speed domino logic with improved cascode keeper circuit comprises an OR gate.

5. The high-speed domino logic with improved cascode keeper circuit of claim 1, wherein;

said first supply voltage is Vdd and said second supply voltage is ground.

6. The high-speed domino logic with improved cascode keeper circuit of claim 5, wherein;

said first transistor, said second transistor, and said fourth transistor are PFETs.

7. The high-speed domino logic with improved cascode keeper circuit of claim 6, wherein;

said third transistor is an NFET.

8. A high-speed domino logic with improved cascode keeper circuit comprising:

a first supply voltage;

a second supply voltage;

a first clock signal;

a high-speed domino logic with improved cascode keeper OUT terminal;

an inverter delay element, said inverter delay element having an inverter delay element input terminal coupled to said first clock signal and an inverter delay element output terminal;

a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode, said first clock signal being coupled to said first transistor control electrode, said first transistor second flow electrode being coupled to a first node, said first transistor having a first threshold voltage;

a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said second transistor second flow electrode being coupled to said first node, said second transistor control electrode being coupled to said high-speed domino logic with improved cascode keeper OUT terminal, said second transistor having substantially said first threshold voltage;

a logic block, said logic block comprising at least one logic block input terminal and a logic block output terminal;

a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said third transistor first flow electrode being coupled to said logic block output terminal, said third transistor second flow electrode being coupled to said second supply voltage, said third transistor control electrode being coupled to said first clock signal;

a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said first supply voltage being coupled to said fourth transistor first flow electrode, said fourth transistor second flow electrode being coupled to second transistor first flow electrode, said fourth transistor control electrode being coupled to said inverter delay element output terminal;

an inverter, said inverter comprising an inverter input terminal and an inverter output terminal, said inverter input terminal being coupled to said first node, said inverter output terminal being coupled to said OUT terminal of said high-speed domino logic with improved cascode keeper circuit;

wherein,

an inverted and delayed first clock signal is coupled from said inverter delay element output terminal to said fourth transistor control electrode, said inverted and delayed first clock signal being approximately 180 degrees out of phase with said first clock signal and delayed with respect to said first clock signal by a predetermined time.

9. The high-speed domino logic with improved cascode keeper circuit of claim 8, wherein;

said inverter delay element comprises one inverter.

10. The high-speed domino logic with improved cascode keeper circuit of claim 8, wherein;

said inverter delay element comprises three inverters.

11. The high-speed domino logic with improved cascode keeper circuit of claim 8, wherein;

said inverter delay element comprises five inverters.

12. The high-speed domino logic with improved cascode keeper circuit of claim 8, wherein;

said inverter delay element comprises an odd number or inverters.

13. The high-speed domino logic with improved cascode keeper circuit of claim 8, wherein;

said logic block of said high-speed domino logic with improved cascode keeper circuit comprises logic gates.

14. The high-speed domino logic with improved cascode keeper circuit of claim 13, wherein;

said logic block of said high-speed domino logic with improved cascode keeper circuit comprises an AND gate.

15. The high-speed domino logic with improved cascode keeper circuit of claim 13, wherein;

said logic block of said high-speed domino logic with improved cascode keeper circuit comprises an OR gate.

16. The high-speed domino logic with improved cascode keeper circuit of claim 8, wherein;

said first supply voltage is Vdd and said second supply voltage is ground.

17. The high-speed domino logic with improved cascode keeper circuit of claim 16, wherein;

said first transistor, said second transistor, and said fourth transistor are PFETs.

18. The high-speed domino logic with improved cascode keeper circuit of claim 17, wherein;

said third transistor is an NFET.

19. A high-speed domino logic with improved cascode keeper circuit comprising:

a first supply voltage, said first supply voltage being VDD;

a second supply voltage, said second supply voltage being ground;

a first clock signal;

a high-speed domino logic with improved cascode keeper OUT terminal;

an inverter delay element, said inverter delay element having an inverter delay element input terminal coupled to said first clock signal and an inverter delay element output terminal, said inverter delay element comprising an odd number of inverters;

a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode, said first clock signal being coupled to said first transistor control electrode, said first transistor second flow electrode being coupled to a first node, said first transistor having a first threshold voltage;

a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said second transistor second flow electrode being coupled to said first node, said second transistor control electrode being coupled to said high-speed domino logic with improved cascode keeper OUT terminal, said second transistor having substantially said first threshold voltage;

a logic block, said logic block comprising at least one logic block input terminal and a logic block output terminal;

a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said third transistor first flow electrode being coupled to said logic block output terminal, said third transistor second flow electrode being coupled to said second supply voltage, said third transistor control electrode being coupled to said first clock signal;

a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said first supply voltage being coupled to said fourth transistor first flow electrode, said fourth transistor second flow electrode being coupled to second transistor first flow electrode, said fourth transistor control electrode being coupled to said inverter delay element output terminal;

an inverter, said inverter comprising an inverter input terminal and an inverter output terminal, said inverter input terminal being coupled to said first node, said inverter output terminal being coupled to said OUT terminal of said high-speed domino logic with improved cascode keeper circuit;

wherein,

an inverted and delayed first clock signal is coupled from said inverter delay element output terminal to said fourth transistor control electrode, said inverted and delayed first clock signal being approximately 180 degrees out of phase with said first clock signal and delayed with respect to said first clock signal by a predetermined time.

20. The high-speed domino logic with improved cascode keeper circuit of claim 19, wherein;

said first transistor, said second transistor, and said fourth transistor are PFETs.

21. The high-speed domino logic with improved cascode keeper circuit of claim 20, wherein;

said third transistor is an NFET.