Plane decoding method and device for three dimensional memories

• US 6,906,940 B1
• Filed: 02/12/2004
• Issued: 06/14/2005
• Est. Priority Date: 02/12/2004
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, DANG T
• Application Number:
  US10/779,147
• Time in Patent Office: 488 Days
• Field of Search: 365/63, 365/185.05, 365/51, 365/225.7, 365/163, 365/185.18
• US Class Current: 365/63
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/30 having the source region and the drain region on the same level, e.g. lateral transistors

Abstract

A multi-layer memory device is provided. The multi-layer memory device includes multiple layers of memory core cells. A word plane electrically connecting each first active terminal of the multiple layers of the memory core cells intersected by the word plane is included. A drain plane substantially orthogonal to the word plane is provided. The drain plane electrically connects each second active terminal of the multiple layers of the memory core cells intersected by the drain plane. A source plane substantially orthogonal to both the word plane and the drain plane is included. The source plane electrically connects each third active terminal of the memory core cells within a single level. In one embodiment, the memory core cells are defined by a device having three active terminals.

Claims

1. A multi-layer memory device, comprising:

multiple layers of memory core cells;

a word plane electrically connecting each first active terminal of the multiple layers of the memory core cells intersected by the word plane;

a drain plane substantially orthogonal to the word plane, the drain plane electrically connecting each second active terminal of the multiple layers of the memory core cells intersected by the drain plane; and

a source plane substantially orthogonal to both the word plane and the drain plane, the source plane electrically connecting each third active terminal of the memory core cells within a single level.

2. The multi-layer memory device of claim 1, further comprising:

via holes interconnecting each source plane, wherein an axis associated with each via hole of a first source plane are substantially aligned with an axis associated with each corresponding via hole of a second source plane.

3. The multi-layer memory device of claim 1, wherein each of the memory core cells include a device having three active terminals, the device being one of a Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET), a Bipolar Junction Transistor (BJT), and a Single Electron Device (SET).

4. The multi-layer memory device of claim 1, wherein the word plane functions as an x-decoder.

5. The multi-layer memory device of claim 1, wherein the drain plane functions as an y-decoder.

6. The multi-layer memory device of claim 1, wherein the source plane functions as a z-decoder.

7. The multi-layer memory device of claim 1, wherein each second active terminal of the multiple layers is connected to a state change element.

8. The multi-layer memory device of claim 7, wherein the state change element is selected from the group consisting of an antifuse, a fuse and a chalcogenide element.

9. The multi-layer memory device of claim 1, wherein each first active terminal of adjacent levels shares a word plane line.

12. The method of claim 1 wherein the method operation of applying a first voltage to the word plane includes,

applying a voltage of about 3 volts.

10. A plane decoding method for a multi-layer memory device, comprising:

defining a source plane in electrical communication with first active terminals associated with memory core cells within a level of the multi-layer memory device;

interconnecting second active terminals associated with memory core cells of the multi-layer memory device with a word plane intersecting each level of the multi-layer memory device; and

interconnecting third active terminals associated with memory core cells of the multi-layer memory device with a drain plane intersecting each level of the multi-layer memory device.

11. The method of claim 10, further comprising:

applying a first voltage to the word plane;

applying a second voltage to the drain plane; and

accessing a value stored within a memory core cell associated with an intersection of the source plane, the word plane and the drain plane.

13. The method of claim 11, wherein the method operation of applying a second voltage to the drain plane includes,

applying a voltage of about 1 volt.

14. The method of claim 10, further comprising:

including a state change element with each of the third active terminals.

15. The method of claim 14, wherein the state change element is selected from the group consisting of a fuse, an antifuse, and chalcogenide material.

16. The method of claim 14, further comprising:

applying a current to the state change element to program a memory core cell associated with the state change element.

18. The method of claim 16, wherein the method operation of applying a voltage to first and second terminals associated with each of the memory core cells of the second plane and the third plane includes,

applying a first voltage to the second plane of memory core cells;

and

applying a second voltage to the third plane of memory core cells.

19. The method of claim 18, wherein the first voltage is greater than the second voltage.

17. A method for accessing a memory core cell of a multi-layer memory device, comprising:

defining a first plane of memory core cells associated with a single level of the multi-layer memory device;

defining a second plane of memory core cells associated with multiple layers of the multi-layer memory device, the second plane being substantially orthogonal to the first plane;

defining a third plane of memory core cells associated with the multiple layers of the multi-layer memory device, the third plane being substantially orthogonal to both the first plane and the second plane; and

applying a voltage to first and second terminals associated with each of the memory core cells of the second plane and the third plane.

20. The method of claim 17, wherein each memory core cell is configured to incorporate three active terminals.

21. The method of claim 17, further comprising:

applying a current to the identified memory core device; and

in response to applying the current, the method includes,

initiating a resistance change of a state change element associated with a third terminal of the memory core cell.

22. The method of claim 21, wherein the state change element is selected from the group consisting of a fuse, an antifuse, and a phase change material.

23. The method of claim 22 wherein the phase change material is chalcogenide.