Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low supply-voltage technologies

• US 6,906,957 B2
• Filed: 09/12/2003
• Issued: 06/14/2005
• Est. Priority Date: 06/12/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Signorello, Alfredo, Conte, Antonino, Giudice, Gianbattista Lo
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/662,151
• Publication Number:
  US 20040057291A1
• Time in Patent Office: 641 Days
• Field of Search: 365/185.2, 365/205, 365/185.22, 365/185.21, 365/207, 365/189.07, 365/189
• US Class Current: 365/185.2
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Claims

1. A circuit for reading a memory cell, the circuit comprising:

a read node operable to receive a read current from the memory cell;

a first current source operable to provide a first bias current to the read node;

a first transistor having a control terminal and a first conduction terminal coupled to the read node;

a reference node;

a reference generator operable to provide a reference current to the reference node;

a second current source operable to provide a second bias current to the reference node; and

a second transistor having a control terminal coupled to the read node and having a first conduction terminal coupled to the reference node.

2. The circuit of claim 1, further comprising:

first and second supply nodes;

wherein the first and second current sources are coupled to the first supply node; and

wherein the first and second transistors each have a respective second conduction terminal coupled to the second supply node.

3. The circuit of claim 1 wherein the first bias current equals the second bias current.

4. The circuit of claim 1 wherein:

the first and second current sources each comprise a respective PMOS transistor; and

the first and second transistors each comprise a respective NMOS transistor.

5. The circuit of claim 1, further comprising:

a third transistor having a control terminal and a conduction terminal coupled to the read node; and

a fourth transistor having a control terminal and a conduction terminal coupled to the reference node.

6. The circuit of claim 1, further comprising:

a bias generator operable to generate a bias voltage; and

wherein the first and second current sources are operable to generate the first and second bias currents in response to the bias voltage.

7. The circuit of claim 1, further comprising a comparator having first and second input terminals respectively coupled to the read and reference nodes.

8. The circuit of claim 1, further comprising a precharger coupled to the read node.

9. A method for reading a memory cell, the method comprising:

sourcing a first bias current to a read node;

sinking a read current from the read node;

sinking from the read node a first difference current that is inversely proportional to the read current;

sourcing a second bias current to a reference node;

sinking a reference current from the read node; and

sinking from the reference node a second difference current that is inversely proportional to the read current.

10. The method of claim 9 wherein the first bias current equals the second bias current.

11. The method of claim 9, further comprising comparing a voltage on the read node to a voltage on the reference node to determine a data value stored in the memory cell.

12. The method of claim 9, further comprising sinking from the read node a third difference current that is inversely proportional to the read current.

13. The method of claim 9, further comprising sinking from the reference node a third difference current that is proportional to the read current.