Erase block data splitting
First Claim
Patent Images
1. A Flash memory system comprising:
- at least one Flash memory device, wherein the at least one Flash memory device contains a memory array with a plurality of floating gate memory cells arranged in a plurality of erase blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of sectors, and each sector contains a user data area and an overhead data area;
wherein the erase blocks of the at least one Flash memory device are arranged in pairs into a plurality of super blocks; and
a control circuit adapted to control data accesses to the sectors of the erase block pair of a selected super block such that user data access and overhead data accesses are directed to differing erase blocks of the super block.
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Abstract
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.
93 Citations
50 Claims
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1. A Flash memory system comprising:
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at least one Flash memory device, wherein the at least one Flash memory device contains a memory array with a plurality of floating gate memory cells arranged in a plurality of erase blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of sectors, and each sector contains a user data area and an overhead data area;
wherein the erase blocks of the at least one Flash memory device are arranged in pairs into a plurality of super blocks; and
a control circuit adapted to control data accesses to the sectors of the erase block pair of a selected super block such that user data access and overhead data accesses are directed to differing erase blocks of the super block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A non-volatile memory device comprising:
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a memory array containing a plurality of floating gate memory cells arranged into a plurality of sectors in a plurality of erase blocks, each sector containing a user data area and an overhead area;
wherein the plurality of erase blocks are arranged in pairs into a plurality of super blocks; and
wherein non-volatile memory device is adapted to execute a data access such that a user data area of a selected first sector of a first erase block of a super block pair also accesses an overhead data area of an associated first sector of a second erase block of the erase block pair of the super block. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A Flash memory device comprising:
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a memory array with a plurality of floating gate memory cells arranged in a plurality of erase blocks, wherein the erase blocks are arranged in pairs into a plurality of super blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of sectors, and each sector contains a user data area and an overhead data area; and
a control circuit adapted to perform data accesses to the sectors of the erase block pair of a super block such that user data access and overhead data accesses are directed to differing erase blocks of the super block. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A method of operating a Flash memory system comprising:
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receiving a memory access request;
accessing a user data area of a sector of an erase block of a plurality of erase blocks of one or more Flash memory devices; and
concurrently accessing an overhead data area of a sector of an associated erase block of the plurality of erase blocks. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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36. A method of operating a Flash memory device comprising:
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receiving a memory access request;
accessing a user data area of a sector of an erase block of a plurality of erase blocks of a Flash memory array; and
accessing an overhead data area of a sector of an associated erase block of the plurality of erase blocks in response to accessing the user data area of the erase block. - View Dependent Claims (37, 38, 39, 40)
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41. An address control circuit comprising:
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a control circuit coupled to a host interface;
a first and second address registers coupled to the control circuit;
an address multiplexer coupled to the first and second address registers and to a Flash memory interface; and
wherein the address control circuit is adapted to load a data access request containing a data address from the host interface and address sequentially addressed Flash memory physical sectors of a selected superblock as data is accessed by a host, where the superblock contains a first and second erase blocks. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49)
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50. A NAND Flash memory system comprising:
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at least one NAND Flash memory device, wherein the at least one Flash memory device contains a NAND architecture memory array with a plurality of floating gate memory cells arranged in a plurality of erase blocks, and wherein each erase block of the plurality of erase blocks contains a plurality of physical sectors, and each physical sector contains a user data area and an overhead data area;
wherein the erase blocks of the at least one NAND Flash memory device are arranged in pairs into a plurality of super blocks;
a control circuit adapted to control data accesses to the physical sectors of the erase block pair of a selected super block; and
wherein the plurality of physical sectors of each erase block in the super block are sequentially addressed, with one erase block holding even addressed physical sectors and the other erase block holding odd addressed physical sectors, and wherein the control circuit is adapted to access the overhead data area of a physical sector m+1 when a user data area of a selected physical sector m is accessed.
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Specification