Packet processing device

• US 6,907,042 B1
• Filed: 04/19/2000
• Issued: 06/14/2005
• Est. Priority Date: 05/18/1999
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Oguchi, Naoki
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): HO, CHUONG T
• Application Number:
  US09/552,135
• Time in Patent Office: 1,882 Days
• Field of Search: 370471-474, 370/394, 370/235, 370/230, 370/232, 370/389, 370412-417, 370/392, 370/401, 370/418, 370/419, 370/422, 370/428, 370/429, 370/469, 370/470, 709/250, 709/236, 709/238, 709/232, 709/225, 709/228
• US Class Current: 370/412
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9026 Single buffer per packet
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level

Abstract

A packet processing device in which a receiving buffer free space notifying portion notifies a free space of a receiving buffer, an accumulation condition determining portion determines a size of a big packet based on the free space, and a reassembly buffer processor reassembles a plurality of receiving packets into a single big packet to be transmitted to the receiving buffer. A backward packet inclusive information reading circuit for detecting the free space based on information within a backward packet from the upper layer may be used as the receiving buffer free space notifying portion. Also, an application layer may be used as the upper layer so that the big packet is transmitted not through a buffer of a transport layer but directly to the receiving buffer.

Claims

1. A packet processing device for processing a layered communication protocol comprising:

a receiving buffer of an upper layer,

first means notifying a free space of the receiving buffer,

second means reassembling a plurality of receiving packets into a single big packet, based on the free space, to be transmitted to the receiving buffer, and

third means determining a size of the big packet based on the free space.

2. The packet processing device as claimed in claim 1 wherein the first means is included in the upper layer and notifies the free space to the third means.

3. The packet processing device as claimed in claim 1 wherein the first means comprises a backward packet inclusive information reading circuit detecting the free space based on information within a backward packet from the upper layer.

4. The packet processing device as claimed in claim 2 wherein the upper layer comprises a transport layer.

5. The packet processing device as claimed in claim 2 wherein the upper layer comprises an application layer and the big packet is transmitted not through a buffer of a transport layer but directly to the receiving buffer.

6. The packet processing device as claimed in claim 1, further comprising a connection identifying circuit identifying a connection of the receiving packets,

the second means reassembling the big packet for each connection based on identification information of the identifying circuit.

7. The packet processing device as claimed in claim 1, further comprising a checksum calculating circuit adding a checksum to the big packet.

8. The packet processing device as claimed in claim 1 wherein the third means has a timer for giving the second means instructions for transmitting the big packet to the receiving buffer when a predetermined time elapses.

9. The packet processing device as claimed in claim 1 wherein the third means gives the second means instructions for assigning the big packet to the receiving buffer at a time when the big packet attains a size for issuance of an acknowledgement packet from the upper layer.

10. The packet processing device as claimed in claim 1 wherein the second means assembles the big packet with a first receiving packet including a header and subsequently received packets whose headers are deleted.

11. The packet processing device as claimed in claim 1, further comprising means immediately transmitting the receiving packet to the receiving buffer without storing the receiving packet in the second means when the receiving packet is a non-accumulation packet.

12. The packet processing device as claimed in claim 1, further comprising an L3 switch which has a packet transfer function in a network layer made in a hardware form and transmits a plurality of receiving packets addressed to itself to the second means.

13. An NIC device comprising the packet processing device according to claim 1 which transmits a plurality of receiving packets addressed to itself to the second means.