Empirical data based test optimization method

• US 6,907,378 B2
• Filed: 09/26/2002
• Issued: 06/14/2005
• Est. Priority Date: 09/26/2002
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Stirrat, Susan, Wu, Kang
• Primary Examiner(s): Tsai, Carol S. W.
• Application Number:
  US10/255,480
• Publication Number:
  US 20040061517A1
• Time in Patent Office: 992 Days
• Field of Search: 702/84, 702/108, 702/119, 700/121, 714 5- 7, 714/703, 714/723, 714/724, 714/726, 714/736, 714/738, 324/765, 324/73.1, 365/200, 365/201
• US Class Current: 702/119
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability

Abstract

A test method for the detection of redundant tests and inefficient tests (RITs) used for testing integrated circuits (ICs) and a subsequent optimization of test complexity and test time duration. Empirical data from an execution of all tests of interest in a test plan, flow or suite of tests is collected. The empirical data is collected without stopping at errors. This empirical data is then used to determine the identity of one or more redundant and/or inefficient tests in the test plan. In order to reduce testing time and optimize the test flow, one of more of the following occurs. Redundant tests may be selectively removed, inefficient tests may be re-ordered to allow more efficient tests to be executed earlier in the test flow of the ICs, or some combination of this. RIT information is thus used to optimize the test flow, resulting in a reduction in test complexity and in test duration.

Claims

1. A method for optimized testing of integrated circuits (ICs), comprising:

executing a first test sequence comprising a plurality of tests to test a first plurality of integrated circuit (ICs) and to generate a statistically significant test result comprising one or more test failures, wherein executing the first test sequence does not stop as the one or more test failures of the first plurality of ICs are generated during execution of the first test sequence;

analyzing the one or more test failures to identify one or more redundant and inefficient tests (RITs) in the plurality of tests of the first test sequence; and

generating a second test sequence that is optimized with respect to the first test sequence by performing at least one of removing and reordering at least one of the one or more identified RITs.

2. The method of claim 1, wherein each RIT of the one or more RITs is one of a redundant test and an inefficient test and performing at least one of removing and reordering the one or more identified RITs to generate the second test sequence further comprises for the at least one of the one or more identified RITs:

removing the RIT from the second test sequence if the RIT is a redundant test; and

reordering the RIT to be executed later in the second test sequence than it was executed in the first test sequence if the RIT is an inefficient test.

3. The method of claim 1, wherein each RIT of the one or more RITs is one of a redundant test and an inefficient test and performing at least one of removing and reordering the one or more identified RITs to generate the second test sequence further comprises for each identified RIT:

removing the RIT from the second test sequence if the RIT is a redundant test; and

reordering the RIT to be executed after a test of the first plurality of tests that is not one of the one or more identified RITs.

4. The method of claim 3, wherein the test that is not one of the one or more identified RITs is more efficient than the RIT.

5. The method of claim 1, wherein analyzing the one or more test failures to identify one or more redundant and efficient tests of the first test sequence further comprises:

identifying one or more redundant tests of the first test sequence; and

wherein generating the second test sequence further comprises;

removing the one or more redundant tests of the first test sequence to generate the second test sequence having a plurality of tests that is fewer than the plurality of tests of the first test sequence.

6. The method of claim 1, wherein analyzing the one or more test failures to identify one or more redundant and efficient tests of the first test sequence further comprises:

identifying one or more inefficient tests of the first test sequence; and

wherein generating the second test sequence further comprises;

ordering the one or more identified inefficient tests in the second test sequence to occur later in the second test sequence than they occurred in the first test sequence.

7. The method of claim 1, further comprising:

executing the second test sequence on a second plurality of ICs, wherein execution of the second test sequence may selectively stop upon generation of one or more test failures of the second plurality of ICs.

8. A method of carrying out a computer assisted function on a general-purpose computer for optimized testing of integrated circuits (ICs) in accordance with a set of instructions, comprising:

instructions for executing a first test sequence comprising a plurality of tests to test a first plurality of integrated circuit (ICs) and to generate a statistically significant test result comprising one or more test failures, wherein executing the first test sequence does not stop as the one or more test failures of the first plurality of ICs are generated during execution of the first test sequence;

instructions for analyzing the one or more test failures to identify one or more redundant and inefficient tests (RITs) in the plurality of tests of the first test sequence; and

instructions for generating a second test sequence that is optimized with respect to the first test sequence by performing at least one of removing and reordering at least one of the one or more identified RITs.

9. The method of claim 8, wherein each RIT of the one or more RITs is one of a redundant test and an inefficient test and performing at least one of removing and reordering the one or more identified RITs to generate the second test sequence further comprises for the at least one of e one or more identified RITs:

instructions for removing the RIT from the second test sequence if the RIT is a redundant test; and

instructions for reordering the RIT to be executed later in the second test sequence than it was execute in the first test sequence if the RIT is an inefficient test.

10. The method of claim 8, wherein each RIT of the one or more RITs is one of a redundant test and an inefficient test and performing at least one of removing and reordering the one or more identified RITs to generate the second test sequence further comprises for each identified RIT:

instructions for removing the RIT from the second test sequence if the RIT is a redundant test; and

instructions for reordering the RIT to be executed after a test of the first plurality of tests that is not one of the one or more identified RITs.

11. The method of claim 10, wherein the test that is not one of the one or more identified RITs is more efficient than the RIT.

12. The method of claim 8, wherein analyzing the one or more test failures to identify one or more redundant and efficient tests of the first test sequence further comprises:

instructions for identifying one or more redundant tests of the first test sequence; and

wherein generating the second test sequence further comprises;

instructions for removing the one or more redundant tests to generate the second test sequence having a plurality of tests that is fewer than the plurality of tests of the first test sequence.

13. The method of claim 8, wherein analyzing the one or more test failures to identify one or more redundant and efficient tests of the first test sequence further comprises:

instructions for identifying one or more inefficient tests of the first test sequence; and

wherein generating the second test sequence further comprises;

instructions for ordering the one or more identified inefficient tests in the second test sequence to occur later in the second test sequence than they occurred in the first test sequence.

14. The method of claim 8, further comprising:

instructions for executing the second test sequence on a second plurality of ICs, wherein execution of the second test sequence may selectively stop upon generation of one or more test failures of the second plurality of ICs.

15. A method for optimized testing of integrated circuits (ICs), comprising:

executing a first test sequence comprising a plurality of tests to test a first plurality of integrated circuits (ICs) and to generate a statistically significant test result comprising one or more test failures, wherein executing the first test sequence does not stop as the one or more test failures of the first plurality of ICs are generated during execution of the first test sequence;

analyzing the one or more test failures to identify one or more redundant tests and one or more inefficient tests in the plurality of tests of the first test sequence; and

generating a second test sequence that is optimized with respect to the first test sequence by removing one or more of the redundant tests from the first test sequence and reordering one or more of the inefficient tests in the first test sequence.

16. The method of claim 15, wherein reordering one or more of the inefficient tests comprises ordering the one or more inefficient tests to occur later in the second test sequence than they ocurred in the first test sequence.

17. The method of claim 15, wherein reordering one or more of the inefficient tests comprises reordering the one or more of the inefficient tests to be executed after one or more tests that are not identified as inefficient.

18. The method of claim 15, further comprising:

executing the second test sequence on a second plurality of ICs, wherein execution of the second test sequence may selectively stop upon generation of one or more test failures of the second plurality of ICs.

19. A method of carrying out a computer assisted function on a general-purpose computer for optimized testing of integrated circuits (ICs) in accordance with a set of instructions, comprising:

instructions for executing a first test sequence comprising a plurality of tests to test a first plurality of integrated circuits (ICs) and to generate a statistically significant test result comprising one or more test failures, wherein executing the first test sequence does not stop as the one or more test failures of the first plurality of ICs are generated during execution of the first test sequence;

instructions for analyzing the one or more test failures to identify one or more redundant tests and one or more inefficient tests in the plurality of tests of the first test sequence; and

instructions for generating a second test sequence that is optimized with respect to the first test sequence by removing one or more of the redundant tests from the first test sequence and reordering one or more of the inefficient tests in the first test sequence.

20. The method of claim 19, wherein reordering one or more of the inefficient tests comprises instructions for ordering the one or more inefficient tests to occur later in the second test sequence than they occurred in the first test sequence.

21. The method of claim 19, wherein reordering one or more of the inefficient tests comprises instructions for reordering the one or more of the inefficient tests to be executed after one or more tests that are not identified as inefficient.

22. The method of claim 19, further comprising:

instructions for executing the second test sequence on a second plurality of ICs, wherein execution of the second test sequence may selectively stop upon generation of one or more test failures of the second plurality of ICs.

23. The method of claim 19, wherein executing the first test sequé

nce does not stop as the one or more test failures of the first plurality of ICs are generated during execution of the first test sequence.