Memory defect redress analysis treating method, and memory testing apparatus performing the method
First Claim
1. A method of analyzing and processing a repair of failure that is carried out in a memory testing apparatus which comprises:
- a failure analysis memory for storing therein failure data representing a failure memory cell or cells of a memory under test having redundancy structure; and
a failure repair analyzing and processing apparatus for analyzing as to whether the failure memory cell or cells of the memory under test can be repaired on the basis of the failure data read out from the failure analysis memory after the testing has been completed, said method comprising the steps of;
reading out failure data respectively from plural specified data bit memory areas of the failure analysis memory in sequence and distributing them to corresponding plural repair analysis units respectively; and
operating concurrently the plural repair analysis units in parallel with each other and causing the units to carry out concurrently their repair analyses and processings for the failure memory cell or cells corresponding to the failure data read out from the failure analysis memory in parallel with each other.
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Accused Products
Abstract
There are provided a failure repair analyzing and processing method and a memory testing apparatus provided with a failure repair analyzing and processing apparatus using this method, that are capable of reducing a time duration required to perform the failure repair analysis and processing for a multi-bit memory having redundancy structure. A plurality of repair analysis units as well as a common failure analysis memory are provided, and these repair analysis units are concurrently operated in parallel with each other, thereby to carry out respective repair analyses and processings for failure memory cells of plural data bits read out from the failure analysis memory in the plural repair analysis units concurrently and in parallel with each other. As a result, a time duration required to execute the failure repair analysis and processing is shortened.
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Citations
9 Claims
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1. A method of analyzing and processing a repair of failure that is carried out in a memory testing apparatus which comprises:
- a failure analysis memory for storing therein failure data representing a failure memory cell or cells of a memory under test having redundancy structure; and
a failure repair analyzing and processing apparatus for analyzing as to whether the failure memory cell or cells of the memory under test can be repaired on the basis of the failure data read out from the failure analysis memory after the testing has been completed, said method comprising the steps of;reading out failure data respectively from plural specified data bit memory areas of the failure analysis memory in sequence and distributing them to corresponding plural repair analysis units respectively; and
operating concurrently the plural repair analysis units in parallel with each other and causing the units to carry out concurrently their repair analyses and processings for the failure memory cell or cells corresponding to the failure data read out from the failure analysis memory in parallel with each other. - View Dependent Claims (2, 3)
- a failure analysis memory for storing therein failure data representing a failure memory cell or cells of a memory under test having redundancy structure; and
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4. A memory testing apparatus comprising:
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a failure analysis memory for storing therein failure data representing a failure memory cell or cells of a memory under test having redundancy structure;
a plurality of repair analysis units, each being constructed such that it specifies any data bit memory area in plural data bit memory areas of the failure analysis memory, reads out failure data stored in the specified data bit memory area in respective failure data stored in the plural data bit memory areas of the failure analysis memory, and analyzes as to whether a memory cell array or arrays associated with the read-out failure data can be repaired or not;
access control means for switching in sequence respective address signals outputted from the plural repair analysis units to apply them to the failure analysis memory in sequence;
data distributing means for distributing respective failure data read out from the plural specified data bit memory areas of the failure analysis memory to the corresponding plural repair analysis units, respectively; and
a control part that controls respective repair analysis and processing operations of the plural repair analysis units. - View Dependent Claims (5, 6, 7, 8, 9)
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Specification