Non-volatile semiconductor memory device

• US 6,907,497 B2
• Filed: 12/20/2002
• Issued: 06/14/2005
• Est. Priority Date: 12/20/2001
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawai, Koichi, Nakamura, Hiroshi, Hosono, Koji, Imamiya, Kenichi, Nakabayashi, Mikito
• Primary Examiner(s): Anderson, Matthew D.
• Application Number:
  US10/325,714
• Publication Number:
  US 20030214853A1
• Time in Patent Office: 907 Days
• Field of Search: 711/103, 365/185.22, 365/185.24, 365/185.29, 365/185.3, 365/185.33
• US Class Current: 711/103
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3463 Circuits or methods to detect overprogrammed nonvolatile memory cells, usually during program verification

Abstract

A non-volatile semiconductor memory device includes a memory cell array, a data hold circuit, and a controller A program control function applies a program voltage to a selected memory cell to let data shift from a first logic state to a second logic state. A program verify control function verifies that a programmed data of the selected memory cell shifted to the second logic state. An erratic program verify control function checks that a threshold voltage of a memory cell to be held in the first logic state does not exceed a third value set as an upper limit value of a variation of the first logic state. An over-program verify control function checks that a threshold voltage of the selected memory cell shifted to the second logic state does not exceed a fourth value set as an upper limit thereof.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell array in which electrically erasable and programmable memory cells are arrayed, each of said memory cells storing therein a first logic state with a threshold voltage lower than or equal to a first value or a second logic state with a threshold voltage higher than or equal to a second value that is higher than said first value;

a data hold circuit for holding program data to be programmed into said memory cell array, said data hold circuit also functioning as a sense amplifier circuit for sensing data as read out of said memory cell array; and

a controller configured to control a program sequence for said memory cell array, wherein said controller has the control functions of;

a program control function for applying, based on said program data loaded into said data hold circuit, a program voltage to a selected memory cell of said memory cell array to let the data shift from said first logic state to said second logic state;

a program verify control function for reading the data programmed into said memory cell array and for verifying that the programmed data of said selected memory cell shifted to said second logic state;

an erratic program verify control function for reading the data programmed into said memory cell array and for checking that the threshold voltage of a memory cell to be held in said first logic state does not exceed a third value set as an upper limit value of a variation of said first logic state; and

an over-program verify control function for reading the data programmed into said memory cell array and for checking that the threshold voltage of said selected memory cell shifted to said second logic state does not exceed a fourth value set as an upper limit thereof.

2. The non-volatile semiconductor memory device according to claim 1, wherein said data hold circuit includes:

a page buffer having first latch circuits for holding read and program data corresponding to one page of said memory cell array; and

a cache having second latch circuits each being data-transferably connected through a transfer gate to a corresponding one of said first latch circuits in said page buffer, for holding said program data as loaded into said page buffer until program completion is determined by said program verify means.

3. The non-volatile semiconductor memory device according to claim 2, wherein said memory device has an on-chip copy mode for reading data of a first page of said memory cell array to said page buffer, logically inverting the read data for transfer to said cache, again transferring the data transferred to said cache toward said page buffer, and programming the data transferred to said page buffer into a second page of said memory cell array.

4. The non-volatile semiconductor memory device according to claim 2, wherein

said memory cell array includes a plurality of NAND cell units laid out in at least one direction, each said NAND cell unit including a serial combination of memory cells having one end connected to a bit line through a first select gate transistor and the other end connected a source line through a second select gate transistor, and wherein

said NAND cell units laid out in said one direction make up a cell block for use as a unit for all-at-once erase, with gates of said first and second select gate transistors being commonly connected to first and second select gate lines respectively and also with the respective control gates of memory cells arrayed in said one direction commonly connected to a word line.

5. The non-volatile semiconductor memory device according to claim 4, wherein said controller further has the functions of:

erase control function for applying an erase voltage to all memory cells within a selected cell block and for causing data thereof to shift from said second logic state to said first logic state; and

erase verify control function for reading data of memory cells within an erased cell block and for verifying completion of shift of the erased data to said first logic state.

6. The non-volatile semiconductor memory device according to claim 5, wherein

the threshold voltage of a memory cell in said first logic state is negative while the threshold voltage of a memory cell in said second logic state is positive, and wherein

a verify read operation controlled by said erase verify control function with respect to said erased cell block is performed by precharging said bit lines to 0V. giving a power supply voltage to said source line, giving a first pass voltage to said first and second select gate lines, and giving a first read voltage to all word lines, causing read currents to flow from said source line to said bit lines through the respective channels of NAND cell units, and detecting charged voltages of said bit lines.

7. The non-volatile semiconductor memory device according to claim 6, wherein said third value is negative, and wherein

a verify read operation controlled by said erratic program verify control function is performed by precharging said bit lines in accordance with logically inverted data of said program data loaded into said data hold circuit, giving a power supply voltage to said source line, giving a first pass voltage to said first and second select gate lines, giving a second read voltage higher than said first read voltage to a word line coupled to memory cells to be checked, and giving said first pass voltage to remaining word lines, causing read currents to flow from said source line to said bit lines through the respective channels of NAND cell units, and detecting charged voltages of said bit lines.

8. The non-volatile semiconductor memory device according to claim 6, wherein said third value is negative, and wherein

a verify read operation controlled by said erratic program verify control function is performed by precharging said bit lines in accordance with logically inverted data of said program data loaded into said data hold circuit, giving a power supply voltage to said source line, giving a first pass voltage to said first select gate line, giving a second pass voltage to lower than said first pass voltage to said second select gate line, giving a second read voltage higher than said first read voltage to a word line coupled to memory cells to be checked, and giving said first pass voltage remaining word lines, causing read currents to flow from said source line to said bit lines through the respective channels of NAND cell units, and detecting charged voltages of said bit lines.

9. The non-volatile semiconductor memory device according to claim 6, wherein said third value is zero or positive, and wherein

a verify read operation controlled by said erratic program verify control function is performed by precharging said bit lines in accordance with said program data loaded into said data hold circuit, then giving a first pass voltage to said first and second select lines, giving a read voltage equivalent to said third value to a word line couple to memory cells to be checked, and giving said first pass voltage to remaining word lines, causing read currents to flow from said bit lines to said source line through the respective channels of NAND cell units, and detecting discharged voltages of said bit lines.

10. The non-volatile semiconductor memory device according to claim 5, wherein a verify read operation controlled by said over-program verify control function is performed by giving a first pass voltage to said first and second select gate lines, and giving a read voltage equivalent to said fourth value to a word line coupled to memory cells to be checked and remaining word lines, thereby detecting whether the NAND cell units each turns on or off.

11. The non-volatile semiconductor memory device according to claim 5, wherein a verify read operation controlled by said erratic program verify control function is performed based on data loaded in said data hold circuit, said data being an it is given from outside of a chip with an address.

12. The non-volatile semiconductor memory device according to claim 5, wherein said memory device has an on-chip copy mode for reading data of a first page of said memory cell array to said page buffer, logically inverting the read data for transfer to said cache, again transferring the data transferred to said cache toward said page buffer, and programming the data transferred to said page buffer into a second page of said memory cell array.

13. The non-volatile semiconductor memory device according to claim 1, wherein a program operation controlled by said program control function and a verify read operation controlled by said program verify control function are recurrently performed until determination of completion of programming all bits of said program data, and wherein a verify read operation controlled by said erratic program verify control function is performed after the determination of program completion.

14. The non-volatile semiconductor memory device according to claim 1, wherein a program operation controlled by said program control function and a verify read operation by said program verify control function are recurrently performed until determination of completion of programming all bits of said program data, and wherein a verify read operation controlled by said erratic program verify control function and a verify read controlled by said over-program verify control function are performed after the determination of program completion.

15. The non-volatile semiconductor memory device according to claim 1, further comprising:

first, second and third status registers for external notification of verify results based on said program verify control function, said erratic program verify control function and said over-program verify control function, respectively.

16. The non-volatile semiconductor memory device according to claim 1, wherein said third value as guaranteed by said erratic program verify control function is net to less than a normal read voltage as given to a control gate of a selected memory cell in a normal read operation.

17. The non-volatile semiconductor memory device according to claim 1, wherein said controller further having the control functions of:

erase control function for applying an erase voltage to memory cells within a block of said memory cell array and for causing all data within said block to shift from said second logic state to said first logic state; and

erase verify control function for reading data of the memory cells within said block and for verifying completion of shift thereof to said first logic state.

18. The non-volatile semiconductor memory device according to claim 17, wherein

the threshold voltage of a memory cell in said first logic state is negative the threshold voltage of a memory cell in said second logic state is positive, and wherein

a verify read operation controlled by said erase verify control function is performed by precharging a bit line connected to a drain of said memory cell array at a specified voltage, applying a prespecified read voltage to a control gate of a memory cell to be checked, causing a read current to flow from a source or said memory cell to its drain, and then detecting a charged voltage of said bit line.

19. The non-volatile semiconductor memory device according to claim 1, wherein

the threshold voltage of a memory cell in said first logic state is negative, the threshold voltage of a memory cell in said second logic state is positive, and said third value is negative, and wherein

a verify read operation controlled by said erratic program verify control function is performed by precharging a bit line connected to a drain of said memory cell array in accordance with logically inverted data of said program data as loaded into said data hold circuit, applying a prespecified read voltage to a control gate of a memory cell to be checked, causing a read current to flow from a source of said memory cell to its drain, and detecting a charged voltage of said bit line.

20. The non-volatile semiconductor memory device according to claim 1, wherein

the threshold voltage of a memory cell in said first logic state is negative, the threshold voltage of a memory cell in said second logic state is positive, and said third value is negative, and wherein

a verify read operation controlled by said erratic program verify control function is performed by precharging a bit line coupled to a drain of said memory cell array in accordance with said program data loaded into said data hold circuit, applying a read voltage used during normal reading to a control gate of a memory cell to be checked, causing a read current to flow from a drain of said memory cell to its source, and detecting a discharged voltage of said bit line.

21. The non-volatile semiconductor memory device according to claim 1, wherein

the threshold voltage of a memory cell in said first logic state is negative, the threshold voltage of a memory cell in said second logic state is positive, and said third value is zero or positive, and wherein

a verify read operation controlled by said erratic program verify control function is performed by precharging a bit line coupled to a drain of said memory cell array in accordance with said program data loaded into said data hold circuit, applying a read voltage equivalent to said third value to a control gate of a memory cell to be checked, causing a read current to flow from a drain of said memory cell to its source, and detecting a discharged voltage of said bit line.

22. The non-volatile semiconductor memory device according to claim 1, wherein a verify read operation controlled by said over-program verify control function is detecting whether a memory cell turns on or off while giving a read voltage equivalent to said fourth value to a control gate of a memory cell to be checked.