System for recovering received data with a reliable gapped clock signal after reading the data from memory using enable and local clock signals

• US 6,907,541 B1
• Filed: 11/07/2000
• Issued: 06/14/2005
• Est. Priority Date: 11/07/2000
• Status: Expired due to Fees

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Padmanabhan, Ramesh, Sindhu, Pradeep, Verwillow, Eric M.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): WANG, ALBERT C
• Application Number:
  US09/706,752
• Time in Patent Office: 1,680 Days
• Field of Search: 713/503, 375/372, 370/300, 370/503, 710/57
• US Class Current: 713/503
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 2205/061 Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
• CPC Class Codes: G06F 2205/126 Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag
• CPC Class Codes: G06F 5/12 Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations

Abstract

A system for reliably receiving data includes a memory, write logic, and read logic. The write logic receives data and an unreliable clock signal and writes the data to the memory using the unreliable clock signal. The read logic generates a gapped clock signal and reads the data from the memory using the gapped clock signal. The read logic generates the gapped clock signal by turning on and off a constant local clock signal.

Claims

1. A system for reliably receiving data, comprising:

a memory;

write logic configured to receive data and an unreliable clock signal and write the data to the memory using the unreliable clock signal; and

read logic configured to generate a data enable signal and a gapped clock signal that is generated by turning on and off a constant local clock signal, the gapped clock signal being used to recover the data, the read logic comprising;

a read register to receive the data enable signal and the constant local clock signal and read the data from the memory based on the data enable signal and the constant local clock signal.

2. The system of claim 1, wherein the write logic includes:

a write register configured to buffer the data, and

a write pointer configured to generate an address for writing the data from the write register into the memory.

3. The system of claim 1, wherein the memory includes a first-in, first-out memory.

4. The system claim 1, wherein the read logic includes:

a gapped clock generator configured to generate the gapped clock signal from the constant local clock signal.

5. The system claim 4, wherein the gapped clock generator includes:

a first state machine configured to generate an enable signal having at least two states and the data enable signal, and

a second state machine configured to turn on and off the constant local clock signal based on the state of the enable signal to generate the gapped clock signal.

6. The system of claim 5, wherein the read logic further includes:

a component configured to determine whether the memory contains data.

7. The system of claim 6, wherein the component includes:

a comparator configured to determine whether the memory contains data by comparing a write address used by the write logic to access the memory to a read address used by the read logic to access the memory.

8. The system of claim 6, wherein the second state machine is configured to turn off the constant local clock signal when the memory contains no data.

9. The system of claim 1, wherein the unreliable clock signal operates at a frequency lower than a frequency of the constant local clock signal;

and

wherein the read logic is configured to compensate for underflow conditions in the memory by turning off the constant local clock signal and disabling the data enable signal.

10. The system of claim 1, wherein the unreliable clock signal operates at a frequency higher than a frequency of the constant local clock signal;

and

wherein the read logic is configured to generate an error signal when overflow conditions occur in the memory.

11. The system of claim 1, wherein the write logic receives no unreliable clock signal;

and

wherein the read logic is configured to start a counter and turn off the constant local clock signal.

12. The system of claim 11, wherein the read logic is further configured to determine that the write logic has received the unreliable clock signal before the counter reaches a predetermined count and turn on the constant local clock signal.

13. The system of claim 11, wherein the read logic is further configured to determine that the counter has reached a predetermined count and turn on the constant local clock signal and disable the data enable signal.

14. The system of claim 13, wherein the read logic is further configured to wait for the write logic to receive the unreliable clock signal before enabling the data enable signal and reading data from the memory.

15. A system for reliably receiving data, comprising:

means for receiving data and an unreliable clock signal;

means for writing the data to a memory using the unreliable clock signal;

means for generating a reliable clock signal by turning on and off a local clock signal;

means for generating a data enable signal;

means for reading the data from the memory using the data enable signal and the local clock signal and without using the reliable clock signal; and

means for recovering the data based on the reliable clock signal.

16. A method for recovering data, comprising:

receiving data and an unreliable clock signal;

writing the data to a memory using the unreliable clock signal;

providing a first state machine to generate a first enable signal and a second enable signal;

providing a second state machine to generate a gapped clock signal by turning on and off a constant local clock signal based on the second enable signal; and

reading the data from the memory using the first enable signal and the constant local clock signal.

17. The method of claim 16, wherein the writing includes:

generating an address for writing the data into the memory.

18. The method of claim 16, further comprising:

determining whether the memory contains data.

19. The method of claim 18, wherein the determining whether the memory contains data includes:

comparing a write address used to access the memory to a read address used to access the memory to determine whether the memory contains data.

20. The method of claim 18, wherein turning on and off the constant local clock signal includes:

stopping the constant local clock signal when the memory contains no data.

21. The method of claim 16, wherein the unreliable clock signal operates at a frequency lower than a frequency of the constant local clock signal;

and

wherein the first and second state machines compensate for underflow conditions in the memory by turning off the constant local clock signal and disabling the first enable signal.

22. The method of claim 16, wherein the unreliable clock signal operates at a frequency higher than a frequency of the constant local clock signal;

and

wherein the second state machine generates an error signal when an overflow condition occurs in the memory.

23. The method of claim 16, further comprising:

receiving no unreliable clock signal; and

wherein the second state machine starts a counter when no unreliable clock signal is received, and turns off the constant local clock signal when no unreliable clock signal is received.

24. The method of claim 23, wherein the second state machine determines that the unreliable clock signal has been received, and turns on the constant local clock signal when the unreliable clock signal has been received before the counter reaches a predetermined count.

25. The method of claim 23, wherein the second state machine determines that the counter has reached a predetermined count, and turns on the constant local clock signal.

26. The method of claim 25, wherein the reading the data from the memory includes:

waiting for the unreliable clock signal to be received before reading data from the memory.

27. A receiver, comprising:

a reliable clock generator configured to;

receive data and an unreliable clock signal,

write the data to a memory using the unreliable clock signal,

generate a reliable clock signal from a constant clock signal,

generate a first enable signal,

read the data from the memory using the first enable signal and the constant clock signal, and

output the data and the reliable clock signal; and

a receiver component configured to receive the data and the reliable clock signal from the reliable clock generator and recover the data based on the reliable clock signal;

where the reliable clock generator includes;

a first state machine configured to generate the first enable signal and a second enable signal, and

a second state machine configured to generate the reliable clock signal in response to the second enable signal.

28. The receiver of claim 27, wherein the reliable clock generator further includes:

a register configured to receive the data read from the memory in response to the first enable signal.

29. The receiver of claim 28, wherein the reliable clock generator further includes:

a component configured to determine whether the memory contains data.

30. The receiver of claim 29, wherein the first state machine is configured to generate the first and second enable signals when the memory contains data.

31. The receiver of claim 29, wherein first state machine is configured to generate neither of the first and second enable signals when the memory contains no data.

32. The receiver of claim 31, wherein the first state machine is further configured to start a counter when the memory contains no data.

33. The receiver of claim 32, wherein the first state machine is further configured to generate the first and second enable signals when the memory contains data before the counter reaches a predetermined count.

34. The receiver of claim 32, wherein the first state machine is configured to determine whether the counter has reached a predetermined count and generate the second enable signal when the counter reaches the predetermined count.

35. The receiver of claim 28, wherein the second state machine is configured to toggle the constant clock signal based on the second enable signal to generate the reliable clock signal.

36. A clock generator, comprising:

a first state machine configured to enter a plurality of states based, at least in part, on whether a memory stores data, within certain ones of the states, the first state machine is configured to generate first and second enable signals, the first enable signal being used to read data from the memory that was written to the memory using an unreliable clock signal; and

a second state machine configured to enter a plurality of states based, at least in part, on the second enable signal, within one of the states, the second state machine is configured to generate a gapped clock signal for reliably recovering the data, within another one of the states, the second machine is configured to generate no gapped clock signal.

37. The clock generator of claim 36, wherein the first state machine is further configured to determine whether the memory contains data.

38. The clock generator of claim 37, wherein the first state machine is configured to generate the first and second enable signals when the memory contains data.

39. The clock generator of claim 37, wherein the first state machine is configured to generate neither of the first and second enable signals when the memory contains no data.

40. The clock generator of claim 39, wherein the first state machine is further configured to start a counter when the memory contains no data.

41. The clock generator of claim 40, wherein the first state machine is further configured to generate the first and second enable signals when the memory contains data before the counter reaches a predetermined count.

42. The clock generator of claim 40, wherein the first state machine is configured to determine whether the counter has reached a predetermined count and generate the second enable signal when the counter reaches the predetermined count.

43. The clock generator of claim 36, wherein the second state machine is configured to toggle a constant local clock signal based on the second enable signal to generate the gapped clock signal.

44. A system, comprising:

a memory;

write logic configured to receive data and an unreliable clock signal and write the data to the memory using the unreliable clock signal; and

read logic including;

a first state machine configured to enter a plurality of states based, at least in part, on whether the memory stores data, within certain ones of the states, the first state machine is configured to generate first and second enable signals, the first enable signal being used to read data from the memory, and

a second state machine configured to enter a plurality of states based, at least in part, on the second enable signal, within one of the states, the second state machine is configured to generate a gapped clock signal for reliably recovering the data, within another one of the states, the second machine is configured to generate no gapped clock signal.