Etch thinning techniques for wafer-to-wafer vertical stacks

• US 6,908,565 B2
• Filed: 12/24/2002
• Issued: 06/21/2005
• Est. Priority Date: 12/24/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Sarah E., List, R. Scott
• Primary Examiner(s): Ahmed, Shamim
• Application Number:
  US10/328,958
• Publication Number:
  US 20040118806A1
• Time in Patent Office: 910 Days
• Field of Search: 216/2, 216/20, 216/33, 216/83, 438/455
• US Class Current: 216/33
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include etching away unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.

Claims

1. A method of fabricating a stacked microelectronic device, comprising:

providing a stacked wafer structure including a first microelectronic wafer attached to a second microelectronic wafer by at least one interconnect layer extending between an active surface of the first microelectronic wafer and an active surface of the second microelectronic wafer, wherein a portion of said first microelectronic wafer is unsupported; and

etching away said first microelectronic wafer unsupported portion by dispensing an etchant to a back surface of said second microelectronic wafer.

2. The method of claim 1, further comprising thinning said first microelectronic wafer to form a first microelectronic wafer thinned back surface.

3. The method of claim 2, further comprising thinning said first microelectronic wafer to a thickness between about 10 and 100 microns.

4. The method of claim 3, further comprising forming at least one conductive via to extend from said first microelectronic wafer thinned back surface to an integrated circuitry layer proximate said first microelectronic wafer active surface.

5. The method of claim 4, further comprising disposing at least one interconnect device on said at least one conductive via.

6. The method of claim 2, wherein thinning said first microelectronic wafer comprises etching a back surface of said first microelectronic wafer during the etching away of said first microelectronic wafer unsupported portion.

7. The method of claim 1, further comprising

thinning said first microelectronic wafer to form a first thinned back surface;

placing said first microelectronic wafer first thinned back surface on a wafer spin processor; and

spinning said wafer spin processor while dispensing said etchant.

8. A method of fabricating a stacked microelectronic device comprising:

providing a first microelectronic wafer having an active surface, a back surface, and at least one edge, said first microelectronic wafer further including an integrated circuitry layer extending from said first microelectronic wafer active surface into said first microelectronic wafer and an interconnect layer on said first microelectronic wafer active surface, and an exclusion zone proximate said first microelectronic wafer edge;

providing a second microelectronic wafer having an active surface and an integrated circuitry layer extending from said second microelectronic wafer active surface into said second microelectronic wafer and an interconnect layer on at least a portion of said second microelectronic wafer active surface;

attaching said first microelectronic wafer interconnect layer to said second microelectronic wafer interconnect layer, wherein a portion of said first microelectronic wafer is unsupported proximate said first microelectronic wafer exclusion zone; and

etching away said first microelectronic wafer unsupported portion by dispensing an etchant to a back surface of said second microelectronic wafer.

9. The method of claim 8, further comprising thinning said first microelectronic wafer.

10. The method of claim 9, further comprising thinning said first microelectronic wafer to a thickness between about 10 and 100 microns.

11. The method of claim 8, wherein thinning said first microelectronic wafer comprises etching a back surface of said first microelectronic wafer during the etching away of said first microelectronic wafer unsupported portion.

12. The method of claim 8, wherein etching away said first microelectronic wafer unsupported portion comprises:

thinning said first microelectronic wafer to form a first thinned back surface;

placing said first microelectronic wafer first thinned back surface on a wafer spin processor; and

spinning said wafer spin processor while dispensing said etchant.

13. The method of claim 12, further including thinning said first microelectronic wafer first thinned back surface to form a second thinned back surface.

14. The method of claim 13, wherein thinning said first microelectronic wafer to form a second thinned back surface comprises etching said first microelectronic wafer first thinned back surface during said etching away of said first microelectronic wafer unsupported portion.

15. The method of claim 14, further comprising forming at least one conductive via to extend from said first microelectronic wafer second thinned back surface to said first microelectronic wafer integrated circuitry layer.

16. The method of claim 15, further comprising disposing at least one interconnect device on said at least one conductive via.

17. A method of fabricating a stacked microelectronic device comprising:

providing a first microelectronic wafer having an active surface, a back surface, and at least one edge, said first microelectronic wafer further including an integrated circuitry layer extending from said first microelectronic wafer active surface into said first microelectronic wafer and an interconnect layer on said first microelectronic wafer active surface, and an exclusion zone proximate said first microelectronic wafer edge;

providing a second microelectronic wafer having an active surface and an integrated circuitry layer extending from said second microelectronic wafer active surface into said second microelectronic wafer and an interconnect layer on at least a portion of said second microelectronic wafer active surface;

attaching said first microelectronic wafer interconnect layer to said second microelectronic wafer interconnect layer, wherein a portion of said first microelectronic wafer is unsupported proximate said first microelectronic wafer exclusion zone;

thinning said first microelectronic wafer to form a first thinned back surface;

placing said first microelectronic wafer first thinned back surface on a wafer spin processor;

spinning said wafer spin processor; and

dispensing an etchant to a back surface of said second microelectronic wafer which etches away said first microelectronic wafer unsupported portion.

18. The method of claim 17, further including thinning said first microelectronic wafer first thinned back surface to form a second thinned back surface.

19. The method of claim 18, wherein thinning said first microelectronic wafer to form a second thinned back surface comprises etching said first microelectronic wafer first thinned back surface during said etching away of said first microelectronic wafer unsupported portion.