MEMS device wafer-level package

• US 6,908,791 B2
• Filed: 04/29/2002
• Issued: 06/21/2005
• Est. Priority Date: 04/29/2002
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Knipe, Richard L., Strumpell, Mark H., Kocian, Thomas A.
• Primary Examiner(s): Geyer, Scott B.
• Application Number:
  US10/135,559
• Publication Number:
  US 20030211654A1
• Time in Patent Office: 1,149 Days
• Field of Search: 438/14, 438/15, 438/17, 438/106, 438/107, 438/110, 438/112, 438/113, 438/116, 438/118, 438/455, 438/456
• US Class Current: 438/110
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 99/004 during manufacturing
• CPC Class Codes: B81C 99/0065 Process control; Yield prediction
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.

Claims

1. A method of manufacturing a semiconductor device comprising:

a) providing a semiconductor wafer;

b) forming a plurality of dies on the semiconductor wafer;

c) placing a bead of adhesive about the perimeter of the at least one die; and

d) attaching a window above at least one individual die of the plurality of dies while the at least one die is still part of the semiconductor wafer.

2. The method of claim 1 wherein the window, the adhesive, and the at least one die, mounted together, form a cavity.

3. The method of claim 2 wherein the cavity is air-tight.

4. The method of claim 2 wherein the cavity is hermetic.

5. The method of claim 1 wherein the at least one die comprises a MEMS device.

6. The method of claim 1 wherein the at least one die comprises an optical device.

7. The method of claim 6 and further comprising projecting images from the optical device wherein the optical device is operable to project an image while still a part of the semiconductor wafer.

8. The method of claim 1 wherein the window is transparent.

9. The method of claim 8 wherein the window is comprised of glass.

10. The method of claim 1 and further comprising performing an inspection of the at least one die before attaching the window.

11. The method of claim 10 wherein the inspection is an electrical test.

12. The method of claim 10 wherein the inspection is a visual test.

13. The method of claim 10 wherein the window is only attached above the at least one die if the at least one die satisfactorily passes the inspection.

14. The method of claim 1, said attaching step comprising covering some, but not all, said dies with said window.

15. A method of manufacturing a semiconductor device comprising:

a) providing a semiconductor wafer;

b) forming a plurality of devices on the semiconductor wafer; and

c) soldering a window above at least one individual device of the plurality of devices while the at least one device is still part of the semiconductor wafer, said window operable to cover said at least one individual device while not covering any of said plurality of devices adjacent to said at least one individual device.

16. The method of claim 15 wherein the at least one device comprises an optical device.

17. The method of claim 15 wherein said device is an optical device, and comprising projecting images from the optical device while still a part of the semiconductor wafer.

18. The method of claim 15 wherein the window is transparent.

19. The method of claim 15 wherein the window is comprised of glass.

20. The method of claim 15 comprising performing an inspection of the at least one device before attaching the window.

21. The method of claim 20 wherein the inspection is an electrical test.

22. The method of claim 20 wherein the inspection is a visual test.

23. The method of claim 20 wherein the window is only attached above the at least one die if the at least one device satisfactorily passes the inspection.

24. The method of claim 15, said soldering step comprising covering some, but not all, said devices with said window.

25. A method of manufacturing a semiconductor device comprising:

a) providing a semiconductor wafer;

b) forming a plurality of dies on the semiconductor wafer;

c) placing a bead of adhesive about the perimeter of the at least one die; and

d) attaching a window above at least one individual die of the plurality of dies, the bead of adhesive being operable to adhere the window to the at least one die while the at least one die is still a part of the semiconductor wafer, said window operable to cover said at least one individual die while not covering any of said plurality of dies adjacent to said at least one individual die.

26. The method of claim 25 wherein the window, the adhesive, and the at least one die, mounted together, form a cavity.

27. The method of claim 25 wherein the window is comprised of glass.

28. The method of claim 25 comprising performing an electrical test on the at least one die before attaching the window.

29. The method of claim 25 comprising performing a visual inspection of the at least one die before attaching the window.

30. The method of claim 25 comprising performing an inspection of the at least one die wherein the window is only attached above the at least one die if the at least one die satisfactorily passes the inspection.