Process for a flash memory with high breakdown resistance between gate and contact
First Claim
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1. A self-aligned process for a flash memory, comprising the steps of:
- depositing a first polysilicon layer, an ONO layer, a second polysilicon layer, a tungsten silicide, and a hard mask layer in a stack over a tunnel oxide layer for a gate structure having a sidewall;
forming a drain and source regions with said gate structure as a mask;
cleaning said tungsten silicide layer with a solution having a high etch selectivity to said tungsten silicide;
performing an annealing process comprising hydrogen and oxygen gases; and
forming a spacer on said sidewall such that buffer gaps are formed in said sidewall between said etched tungsten silicide and said spacer, whereby thermal expansion stress is reduced.
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Abstract
A selfaligned process for a flash memory comprises applying a solution with a high etch selectivity to etch the sidewall of the tungsten silicide in the gate structure of the flash memory during a clean process before forming a spacer for the gate structure. This process prevents the gate structure from degradation caused by thermal stress.
12 Citations
7 Claims
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1. A self-aligned process for a flash memory, comprising the steps of:
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depositing a first polysilicon layer, an ONO layer, a second polysilicon layer, a tungsten silicide, and a hard mask layer in a stack over a tunnel oxide layer for a gate structure having a sidewall;
forming a drain and source regions with said gate structure as a mask;
cleaning said tungsten silicide layer with a solution having a high etch selectivity to said tungsten silicide;
performing an annealing process comprising hydrogen and oxygen gases; and
forming a spacer on said sidewall such that buffer gaps are formed in said sidewall between said etched tungsten silicide and said spacer, whereby thermal expansion stress is reduced. - View Dependent Claims (2, 3)
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4. A self-aligned process for a flash memory, comprising the steps of:
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forming a gate stack including a metal silicide on a tunnel oxide layer;
forming drain and source regions with said gate stack as a mask;
etching a sidewall of said metal silicide;
performing an annealing process comprising hydrogen and oxygen gases; and
forming a spacer for said gate stack such that buffer gaps are formed between said etched sidewall of said metal silicide and said spacer, whereby thermal expansion stress is reduced;
wherein said step of etching a sidewall of said metal silicide comprises applying a solution having a high etch selectivity to said metal silicide. - View Dependent Claims (5, 6, 7)
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Specification
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Current AssigneeMacronix International Co., Ltd.
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Original AssigneeMacronix International Co., Ltd.
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InventorsYang, Lin-Wu, Jeng, Pei-Ren
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Primary Examiner(s)CHEN, JACK S J
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Application NumberUS10/725,556Publication NumberTime in Patent Office566 DaysField of Search438257-267US Class Current438/257CPC Class CodesH01L 29/40114 the electrodes comprising a...
