Support structures for wirebond regions of contact pads over low modulus materials

• US 6,908,841 B2
• Filed: 09/20/2002
• Issued: 06/21/2005
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG, International Business Machines Corporation
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation
• Inventors: Anderson, David, Crabbe, Emmanuel F., Barth, Hans-Joachim, Burrell, Lloyd G., Nye, Henry A. III, Chan, Joseph, Kemerer, Douglas
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/251,453
• Publication Number:
  US 20040058520A1
• Time in Patent Office: 1,005 Days
• Field of Search: 438/612, 438/617, 438/637, 438/638, 438/622, 438/624, 438/926
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).

Claims

1. A method of forming a semiconductor device, comprising:

providing a workpiece comprising a contact pad region having a selected area, at least one integrated circuit being formed within the workpiece;

forming a plurality of low modulus dielectric layers over the workpiece;

forming a plurality of support via groups in said contact pad region, and within each low modulus dielectric layer to provide mechanical support to said low modulus dielectric layers, each one of the support via groups comprising at least three vias, and having a bottom end and a top end;

forming a plurality of support structures within each low modulus dielectric layer in at least the contact pad region, the support structures located at the top ends of the vias and the bottom ends of the vias located over support structures in an adjacent underlying low modulus dielectric layer, and wherein forming the support structures comprises the steps of forming support structures in odd alternating low modulus dielectric layers by disposing a plurality of first conductive lines parallel to one another in a first direction along at least the length of the contact pad bond portion and forming support structures in even alternating low modulus dielectric layers by disposing a plurality of second conductive lines parallel to one another in a second direction alone at least the width of the contact pad bond portion, the second direction being substantially perpendicular to the first direction, wherein forming the support via groups comprises disposing the support vias at the intersection of the first and second conductive lines;

disposing a high modulus dielectric layer over the top of each low modulus dielectric layer; and

forming at least one contact pad in the contact pad region within the high modulus dielectric layer.

2. The method according to claim 1, wherein forming a plurality of support via groups and forming a plurality of support structures comprise a single damascene process.

3. The method according to claim 1, wherein forming a plurality of support via groups and forming a plurality of support structures comprise a dual damascene process.

4. The method according to claim 1, further comprising coupling at least one of the conductive lines to a signal line of an integrated circuit in the workpiece.

5. The method according to claim 1, further comprising forming a signal-conducting line within at least one metallization layer between two adjacent conductive lines, wherein the signal-conducting line is coupled to a signal line of an integrated circuit in the workpiece.

6. The method according to claim 1, further comprising disposing a signal-conducting line within at least one metallization layer between two adjacent first or second conductive lines, and coupling the signal-conducting line to a signal line of an integrated circuit in the workpiece.

7. The method according to claim 1, wherein forming the support structures comprises forming a plurality of discrete support pads.

8. The method according to claim 7, further comprising coupling at least one of the support pads to a signal line of an integrated circuit in the workpiece.

9. The method according to claim 7, further comprising disposing at least one conductive line between two adjacent support pads within the metallization layer, wherein the conductive line is coupled to a signal line of an integrated circuit in the workpiece.

10. The method according to claim 1, further comprising positioning the plurality of support via groups over one another within each low modulus dielectric layer to form a via support stack.

11. The method according to claim 10 wherein each low modulus dielectric layer has a thickness of between about 1 μ

m and about 2.5 μ

m.

12. The method according to claim 1 wherein said high modulus dielectric layer has a thickness of between about 1 μ

m and about 2.5 μ

m.

13. The method according to claim 1 wherein each low modulus dielectric layer has a thickness of between about 1 μ

m and about 2.5 μ

m.

14. The method according to claim 1 wherein at least one group of said plurality of groups carries an electrical current.

15. A method of forming a semiconductor device, comprising:

providing a workpiece comprising a contact pad region having a selected area, at least one integrated circuit being formed within the workpiece;

forming a plurality of low modulus dielectric layers over the workpiece;

forming a plurality of high modulus dielectric layers between each low modulus dielectric layer;

forming a plurality of support via groups in said contact pad region, and within each high modulus dielectric layer, each one of the support via groups comprising at least three vias having a bottom pad and a top end;

forming a plurality of support structures within each low modulus dielectric layer in at least the contact pad region to provide mechanical support to said low modulus dielectric layer, a support structure located at the top ends of at least each via group and the bottom ends of each via group located over a support structure in an adjacent underlying low modulus dielectric layer, and wherein forming the support structures comprises the steps of forming support structures in odd alternating low modulus dielectric layers by disposing a plurality of first conductive lines parallel to one another in a first direction along at least the length of the contact pad bond portion and forming support structures in even alternating low modulus dielectric layers by disposing a plurality of second conductive lines parallel to one another in a second direction along at least the width of the contact pad bond portion, the second direction being substantially perpendicular to the first direction, wherein forming the support via groups comprises disposing the support vias at the intersection of the first and second conductive lines;

disposing a high modulus dielectric layer over each low modulus dielectric layer; and

forming at least one contact pad in the contact pad region within the high modulus dielectric layer.

16. The method according to claim 15, wherein forming a plurality of support via groups and forming a plurality of support structures comprise a single damascene process.

17. The method according to claim 15, wherein forming a plurality of support, via groups and forming a plurality of support structures comprise a dual damascene process.

18. The method according to claim 15, further comprising coupling at least one of the conductive lines to a signal line of an integrated circuit in the workpiece.

19. The method according to claim 15, further comprising forming a signal-conducting line within at least one metallization layer between two adjacent conductive lines, wherein the signal-conducting line is coupled to a signal line of an integrated circuit in the workpiece.

20. The method according to claim 15, wherein the support structures comprises forming a plurality of discrete support pads.

21. The method according to claim 20, further comprising coupling at least one of the support pads to a signal line of an integrated circuit in the workpiece.

22. The method according to claim 20, further comprising disposing at least one conductive line between two adjacent support pads within the metallization layer, wherein the conductive line is coupled to a signal line of an integrated circuit in the workpiece.

23. The method according to claim 15, further comprising positioning the plurality of support via groups over one another within each low modulus dielectric layer to form a via support stack.

24. The method according to claim 15 wherein said high modulus dielectric layer has a thickness of between about 1 μ

m and about 2.5 μ

m.

25. The method of claim 15 wherein at least one group of said plurality of groups carries an electrical current.

26. A method of forming a semiconductor device, comprising:

providing a workpiece comprising a contact pad region having a selected area, at least one integrated circuit being formed within the workpiece;

forming a plurality of low modulus dielectric layers over the workpiece;

forming a plurality of support via groups in said conduct pad region, and within each low modulus dielectric layer to provide support to said low modulus dielectric layers, each one of the support via groups comprising at least three vias, and each via in said plurality of support via groups defining a cross sectional area, and having a bottom end and a top end, the total amount of the cross sectional area of the support vias in each low modulus dielectric layer being at least seven percent (7%) of said selected area of said contact pad region;

forming a plurality of support structures within each low modulus dielectric layer in at least the contact pad region to provide mechanical support to said low modulus dielectric layer, the support structures located at the top ends of the vias and the bottom ends of the vias located over support structures in an adjacent underlying low modulus dielectric layer, and wherein forming the support structures comprises the steps of forming support structures in odd alternating low modulus dielectric layers by disposing a plurality of first conductive lines parallel to one another in a first direction along at least the length of the contact pad bond portion and forming support structures in even alternating low modulus dielectric layers by disposing a plurality of second conductive lines parallel to one another in a second discretion along at least the width of the contact pad bond portion, the second direction being substantially perpendicular to the first direction, wherein forming the support via groups comprises disposing the support vias at the intersection of the first and second conductive lines;

disposing a high modulus dielectric layer over the top low modulus dielectric layer; and

forming at least one contact pad in the contact pad region within the high modulus dielectric layer.

27. The method according to claim 26 wherein the total amount of said cross sectional area of said vias is at least eighteen percent (18%) of said selected area of said contact pad region.

28. The method of claim 26 wherein said high modulus dielectric layer has a thickness of between about 1 μ

m and about 2.5 μ

m.

29. The method according to claim 28 wherein the total amount of said cross sectional area of said vias is at least eighteen percent (18%) of said selected area of said contact pad region.

30. The method of claim 26 further comprising depressing a high modulus dielectric film, between each two adjacent low modulus dielectric layers.

31. The method according to claim 30 wherein the total amount of said cross sectional area of said vias is at least eighteen percent (18%) of said selected area of said contact pad region.

32. The method of claim 26 wherein each low modulus dielectric layer has a thickness of between about 1 μ

m and about 2.5 μ

m.

33. The method according to claim 32 wherein the total amount of said cross sectional area of said vias is at least eighteen percent (18%) of said selected area of said contact pad region.

34. The method of claim 26 further comprising positioning the plurality of support via groups over one another within each low modulus dielectric layer to form a via support stack.

35. The method according to claim 34 wherein the total amount of said cross sectional area of said vias is at least eighteen percent (18%) of said selected area of said contact pad region.

36. The method of claim 26 wherein at least one group of said plurality of groups carries an electrical current.