Method of manufacturing a semiconductor device having an interconnect embedded in an insulating film

• US 6,908,847 B2
• Filed: 12/27/2002
• Issued: 06/21/2005
• Est. Priority Date: 11/15/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Noguchi, Junji, Saito, Tatsuyuki, Imai, Toshinori, Ohashi, Naofumi, Tamaru, Tsuyoshi
• Primary Examiner(s): NGUYEN, THANH T
• Application Number:
  US10/329,831
• Publication Number:
  US 20030109129A1
• Time in Patent Office: 907 Days
• Field of Search: 438/618, 438622-624, 438627-629, 438637-640, 438/631, 438/633, 438643-945, 438653-654, 438/685, 438/688
• US Class Current: 438/627
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

forming a first interlayer insulating film over a semiconductor substrate;

forming a wiring trench in said first interlayer insulating film;

forming a first barrier metal layer over side walls and a bottom surface of said wiring trench;

forming a wiring layer by forming a first conductor layer over said first barrier metal layer so as to embed said wiring trench with said first conductor layer;

forming a capping barrier metal film over a surface of said first conductor layer;

forming a second interlayer insulating film over said first interlayer insulating film;

forming a connecting hole in said second interlayer insulating film, said connecting hole being formed so as to expose at least a part of said capping barrier metal film;

forming a second barrier metal layer over side walls and a bottom surface of said connecting hole; and

forming a plug by forming a second conductor layer over said second barrier metal layer so as to embed said connecting hole with said second conductor layer,

wherein said capping barrier metal film is removed in said step of forming said connecting hole, and is removed only at an overlapping portion of said connecting hole with said wiring trench in the step of forming said connecting hole, and

wherein the method further comprises at least one of the steps of;

heat treating, in an atmosphere containing hydrogen or ammonia, the surface of said first conductor layer exposed after the step of forming said connecting hole;

generating plasma in an atmosphere containing either one of hydrogen or ammonia and a rare gas, and irradiating said surface of said first conductor layer that is exposed, with the plasma; and

sputter etching with a rare gas, said surface of said first conductor layer exposed.

2. A method of manufacturing a semiconductor device according to claim 1, wherein, at the overlapping portion of said wiring trench and said connecting hole, said wiring trench is formed to be greater in area than said connecting hole.

3. A method of manufacturing a semiconductor device according to claim 1, wherein said barrier metal layer is formed from a single layer film of any one of Ta, TaN, TaSiN, W, WN, WSiN, Ti, TiN and TiSiN, or a laminate film obtained by stacking a plurality of any two or greater of Ta, TaN, TaSiN, W, WN, WSiN, Ti, TiN and TiSiN.

4. A method of manufacturing a semiconductor device according to claim 1, wherein said capping barrier metal film is formed from a metal layer comprised mainly of W, WN, WsiN and W, a metal layer comprised mainly of CoWP, CoWB or Co, a single layer film of any one of TiN, TiSiN, Ta, TaN and TaSiN, or a laminate film obtained by stacking any two of said metal layers and single layer films.

5. A method of manufacturing a semiconductor device according to claim 1, wherein said conductor layer is formed from any one of Cu, a metal layer comprised mainly of Cu, Al, a metal layer comprised mainly of Al, Ag and a metal layer comprised mainly of Ag.

6. A method of manufacturing a semiconductor device according to claim 1, wherein said capping barrier metal film is removed so as to expose said first conductor layer.

7. A method of manufacturing a semiconductor device according to claim 1, wherein said second conductor layer is formed in direct contact with said first conductor layer.

8. A method of manufacturing a semiconductor device according to claim 1, wherein said capping barrier metal film is formed by selective growth or preferential growth.

9. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming a first insulating film over a semiconductor substrate;

(b) forming a first wiring layer in said first insulating film;

(c) forming a conductive capping layer over a surface of said first wiring layer by selective growth or preferential growth;

(d) forming a second insulating film over said conductive capping layer and first insulating film;

(e) selectively removing said second insulating film to form a wiring trench and a connecting hole in said second insulating firm, wherein said connecting hole extends from the bottom of said wiring trench toward said conductive capping layer

(f) removing said conductive capping layer formed over the bottom of said connecting hole;

(g) forming a barrier metal film over side walls and the bottom of said wiring trench and side walls and the bottom of said connecting hole; and

(h) forming a conductor layer in said wiring trench and said connecting hole, and

wherein the method further comprises at least one of the steps of;

heat treating, in an atmosphere containing hydrogen or ammonia, the surface of said first wiring layer exposed after the step of forming said connecting hole;

generating plasma in an atmosphere containing either one of hydrogen or ammonia and a rare gas, and irradiating said surface of said first wiring layer, that is exposed, with the plasma; and

sputter etching with a rare gas, said surface of said first wiring layer exposed.

10. A method of manufacturing a semiconductor device according to claim 9, further comprising, between said steps (g) and (h), removing said barrier metal film from the bottom of said connecting hole.

11. A method of manufacturing a semiconductor device according to claim 10, wherein in said barrier metal film formation step, said barrier metal film is formed to be thicker at the bottom of said wiring trench than at the bottom of said connecting hole.

12. A method of manufacturing a semiconductor device according to claim 10, wherein anisotropic etching is employed for the removal of said barrier metal film from the bottom of said connecting hole.

13. A method of manufacturing a semiconductor device according to claim 9, wherein said barrier metal layer is formed from a single layer film of any one of Ta, TaN, TaSiN, W, WN, WSiN, Ti, TiN and TiSiN, or a laminate film obtained by stacking a plurality of any two or greater of Ta, TaN, TaSiN, W, WN, WSiN, Ti, TiN and TiSiN.

14. A method of manufacturing a semiconductor device according to claim 9, wherein said first wiring layer and said conductor layer are formed of a metal layer comprised mainly of copper.

15. A method of manufacturing a semiconductor device according to claim 9, wherein said conductive capping layer is formed from a metal layer comprised mainly of W, WN, WSiN, and W, a metal layer comprised mainly of CoWP, CoWB or Co, a single layer film of any one of TiN, TiSiN, Ta, TaN and TaSiN, or a laminate film obtained by stacking any two of said metal layers and single layer films.

16. A method of manufacturing a semiconductor device according to claim 9, wherein said first and second insulating films are formed of Si and C;

Si, C and O;

Si, O and F;

C and H;

or Si, O, C and H, or, in addition, is porous.

17. A method of manufacturing a semiconductor device, comprising the steps of:

forming a first interlayer insulating film over a semiconductor substrate;

forming a wiring trench in said interlayer insulating film;

forming a first barrier metal layer over side walls and a bottom surface of said wiring trench;

forming a wiring layer by forming a first conductor layer over said first barrier metal layer so as to embed said wiring trench with said first conductor layer,

forming a capping barrier metal film over a surface of said first conductor layer;

forming a second interlayer insulating film over said first interlayer insulating film;

forming a connecting hole in said second interlayer insulating film, said connecting hole being formed so as to expose at least a part of said capping barrier metal film;

forming a second barrier metal layer over side walls and a bottom surface of said connecting hole;

removing said second barrier metal layer from the bottom surface of said connecting hole; and

forming a plug by forming a second conductor layer over said second barrier metal layer so as to embed said connecting hole with said second conductor layer,

wherein said capping barrier metal film is removed in said step of forming said connecting hole, and is removed only at an overlapping portion of said connecting hole with said wiring trench in the step of forming said connecting hole, and

wherein the method further comprises at least one of the steps of;

heat treating, In an atmosphere containing hydrogen or ammonia, the surface of said first conductor layer exposed after the step of removing said second barrier metal layer;

generating plasma in an atmosphere containing either hydrogen or ammonia and a rare gas, and irradiating said exposed surface of said first conductor layer with the plasma; and

cleaning said exposed surface of said first conductor layer with a hydrogen-fluoride-containing solution.