Semiconductor display device and manufacturing method thereof
First Claim
1. A semiconductor device comprising a plurality of thin film transistors formed over a transparent insulating substrate, each of said thin film transistors comprising:
- a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode, wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located over the first layer gate electrode wherein the first layer gate electrode extends beyond a side edge of the second layer gate electrode, wherein a first impurity region is formed in the semiconductor layer below the extending portion of the first layer gate electrode, wherein a second impurity region and the source region or the drain region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer being the outside of a side edge of the first gate electrode, and wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the source region or the drain region.
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Abstract
A semiconductor display device which includes the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask, and thus impurity concentrations of the Lov regions and the Loff regions can be independently controlled. Therefore, the GOLD structure TFT having both the hot carrier resistance and the off-current suppressing effect can be formed and the simplification of a manufacturing process of the semiconductor display device and the improvement of performance thereof are compatible with each other.
98 Citations
22 Claims
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1. A semiconductor device comprising a plurality of thin film transistors formed over a transparent insulating substrate, each of said thin film transistors comprising:
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a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode, wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located over the first layer gate electrode wherein the first layer gate electrode extends beyond a side edge of the second layer gate electrode, wherein a first impurity region is formed in the semiconductor layer below the extending portion of the first layer gate electrode, wherein a second impurity region and the source region or the drain region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer being the outside of a side edge of the first gate electrode, and wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the source region or the drain region. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising a plurality of n-channel thin film transistors formed over a transparent insulating substrate, each of the n-channel thin film transistors comprising:
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a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode, wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located over the first layer gate electrode wherein the first layer gate electrode extends beyond a side edge of the second layer gate electrode, wherein a first impurity region is formed in the semiconductor layer below the extending portion of the first layer gate electrode, wherein a second impurity region and the source region or the drain region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer being the outside of a side edge of the first gate electrode, and wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the source region or the drain region. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising:
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a substrate;
a semiconductor layer formed over the substrate;
a gate insulating film formed over the semiconductor layer;
a gate electrode formed over the semiconductor layer with the gate insulating film interposed therebetween, said gate electrode including a first conductive layer and a second conductive layer formed on the first conductive layer wherein the first conductive layer extends beyond side edges of the second conductive layer;
a pair of first impurity regions formed in the semiconductor layer below the extending portions of the first conductive layer;
a channel region formed in the semiconductor layer between the pair of first impurity regions;
source and drain regions formed in the semiconductor layer;
a pair of second impurity regions formed in the semiconductor layer between the pair of first impurity regions and the source and drain regions, wherein an impurity concentration of the first impurity region is higher than that of the second impurity region and lower than that of the source and drain regions. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification