Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting

• US 6,909,296 B2
• Filed: 03/16/2004
• Issued: 06/21/2005
• Est. Priority Date: 03/19/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Motsiff, William T., Abadeer, Wadgi W.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US10/801,387
• Publication Number:
  US 20040175851A1
• Time in Patent Office: 462 Days
• Field of Search: 324760-766, 324750-753, 324/501, 324/500, 438 14- 18, 702/84
• US Class Current: 324/750.05
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/315 by inductive methods

Abstract

A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any wafer during burn-in/stress. Also provided is a method for implementing the wafer level product burn-in/screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system. Pursuant to a preferred aspect all chips of a wafer are stressed simultaneously without having a probe physically contact any chip during the stress procedure. This concept can be applied to burn-in of product wafers, voltage screen of product wafers, and reliability evaluations of various failure mechanisms.

Claims

1. A method for electrically stressing through a specified voltage at least one semiconductor chip on wafers for controlled contactiess bum-in, voltage screen and reliability evaluation of product wafers, said method comprising:

applying said voltage to said at least one chip for the probing thereof in the absence of physically contacting the chip surface; and

providing a rectangular core of non-magnetic material having electrical wire coils wound thereabout, imparting a magnetically induced voltage at the ends of a wire loop on top of each said chip, including decal masks on a plurality of said wafers positioned centrally on said core, each said decal mask being provided to conduct said magnetically induced voltage to a chip under said decal mask.

2. A method as claimed in claim 1, wherein said magnetically induced voltage utilizes a time-varying magnetic field.

3. A method as claimed in claim 1, wherein each said coil is conducted to a time-varying voltage source so as to generate a magnetic field perpendicular to the surface of each said wafer in the center of said non-magnetic core.

4. A method as claimed in claim 3, wherein electrical wires extend from each said mask to a panel for the direct measurements and verification of the direct voltages present on each of said wafer.

5. A method as claimed in claim 1, wherein said non-magnetic core is constituted of wood.