Nonvolatile memory having bit line discharge, and method of operation thereof

• US 6,909,639 B2
• Filed: 04/22/2003
• Issued: 06/21/2005
• Est. Priority Date: 04/22/2003
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: NexFlash Technologies, Inc. (Winbond Electronics Corporation)
• Inventors: Lee, Poongyeub, Park, Eungjoon, Park, Joo Weon, Han, Kyung Joon
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/421,458
• Publication Number:
  US 20040213048A1
• Time in Patent Office: 791 Days
• Field of Search: 365/185.25, 365/185.11, 365/204, 365/230.03
• US Class Current: 365/185.25
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim (“FN”) tunneling, highly conductive and lengthy bit lines, buried and relatively short sub-bit lines and a programming discharge circuit for controlling spurious voltages on the bit lines that can arise when some of the bit lines are left floating during programming. Discharge control transistor respectively coupled to the bit lines direct current into a discharge section. A discharge section may be provided for each bit line, or shared by all bit lines. The discharge section may be a fixed circuit section for use through the programming process or may be selected from multiple discharge options.

Claims

1. A nonvolatile virtual ground integrated circuit memory array comprising:

a plurality of nonvolatile memory cells;

a plurality of bit lines, the bit lines being coupled to respective subsets of the memory cells; and

a spurious programming voltage discharge circuit coupled to the bit lines and comprising;

a plurality of discharge control elements coupled to the bit lines; and

a discharge section coupled to the discharge control elements.

2. The memory array of claim 1 wherein the discharge control elements are transistors, and the discharge section comprises:

a resistor; and

a diode-connected transistor connected in series with the resistor.

3. The memory array of claim 1 wherein the discharge control elements are transistors, and the discharge section comprises a resistor.

4. The memory array of claim 1 wherein the discharge control elements are transistors, and the discharge section comprises:

a first resistor;

a second resistor connected in series with the first resistor; and

a diode-connected transistor connected in series with the first resistor, the second resistor and the diode-connected transistor being connected in parallel.

5. A nonvolatile virtual ground integrated circuit memory array comprising:

a plurality of nonvolatile memory cells;

a plurality of bit lines, the bit lines being coupled to respective subsets of the memory cells; and

a spurious programming voltage discharge circuit coupled to the bit lines and comprising;

a plurality of discharge control elements coupled to the bit lines;

a plurality of discharge sections; and

a switching circuit having one terminal coupled to the discharge control elements and a plurality of terminals respectively coupled to the discharge sections.

6. The memory array of claim 5 wherein:

at least one of the discharge sections is optimized for discharging spurious voltage from cell leakage; and

at least one of the discharge sections is optimized for discharging spurious voltage from bit line coupling.

7. A nonvolatile virtual ground integrated circuit memory array comprising:

a plurality of nonvolatile memory cells;

a plurality of bit lines, the bit lines being coupled to respective subsets of the memory cells; and

a spurious programming voltage discharge circuit coupled to the bit lines and comprising;

a plurality of discharge control elements coupled to the bit lines; and

a plurality of discharge sections respectively coupled to the discharge control elements.

8. A nonvolatile virtual ground integrated circuit memory array comprising:

a plurality of nonvolatile memory cells;

a plurality of bit lines, the bit lines being coupled to respective subsets of the memory cells and each of the bit lines comprising a main bit line and a plurality of sub-bit lines coupled to the main bit line; and

a spurious programming voltage discharge circuit coupled to the main bit lines.

9. A nonvolatile virtual ground integrated circuit memory array comprising:

a plurality of asymmetrical single transistor floating gate memory cells;

a plurality of main bit lines;

a plurality of sub-bit lines coupled to the memory cells, each of the bit lines being coupled to a subset of the sub-bit lines;

a plurality of discharge control transistors respectively coupled to the bit lines; and

a discharge section coupled to the discharge control elements.

10. A nonvolatile virtual ground integrated circuit memory array comprising:

a plurality of asymmetrical single transistor floating gate memory cells;

a plurality of main bit lines;

a plurality of sub-bit lines coupled to the memory cells, each of the bit lines being coupled to a subset of the sub-bit lines;

a plurality of discharge control transistors respectively coupled to the bit lines;

a plurality of discharge sections wherein at least one of the discharge sections is optimized for discharging spurious voltage from cell leakage, and at least one of the discharge sections is optimized for discharging spurious voltage from bit line coupling; and

a switching circuit having one terminal coupled to the discharge control transistors and a plurality of terminals respectively coupled to the discharge sections.

11. A method of discharging floating bit lines during programming of a nonvolatile virtual ground integrated circuit memory array having a plurality of memory cells, the method comprising:

placing data on selected ones of the bit lines, wherein unselected ones of the bit lines are floated;

apply a programming pulse to selected ones of the memory cells, whereby spurious voltages are coupled to the floated bit lines; and

discharging the spurious voltages from the floated bit lines during at least part of the applying step.

12. The method of claim 11 further comprising repeating the placing, applying and discharging steps to program slower ones of the memory cells.

13. The method of claim 12 wherein:

the initial discharging step is performed with a first discharge option; and

the repeated discharging step is performed with a second discharge option different than the first discharge option.

14. The method of claim 11 further comprising:

performing a verify read of the memory array to obtain verify data;

repeating the placing, applying and discharging steps, wherein the data comprises the verify data.

15. The method of claim 11 wherein the discharging step comprises coupling a discharge circuit section to the floated bit lines during at least part of the applying step.

16. A method of discharging floating bit lines during programming of a nonvolatile virtual ground integrated circuit memory array having a plurality of memory cells, the method comprising:

placing program data on first selected ones of the bit lines, wherein first unselected ones of the bit lines are floated;

apply a first programming pulse to a selected page of the memory cells, wherein first spurious voltages are coupled to the first floated bit lines from the first selected bit lines;

discharging the first spurious voltages from the first floated bit lines;

performing a verify read of the memory array to obtain verify data;

placing the verify data on second selected ones of the bit lines, wherein second unselected ones of the bit lines are floated;

apply a second programming pulse to the selected page of the memory cells, wherein second spurious voltages are coupled to the second floated bit lines from the second selected bit lines; and

discharging the second spurious voltages from the second floated bit lines.

17. The method of claim 16 wherein:

the first spurious voltages discharging step is performed with a first discharge option; and

the second spurious voltages discharging step is performed with a second discharge option different than the first discharge option.

18. The method of claim 16 further comprising repeating the verify read performing step, the verify data placing step, the second programming pulse applying step, and the second spurious voltage discharging step to program slower ones of the memory cells.

19. The method of claim 18 wherein:

the first spurious voltages discharging step is performed with a first discharge option;

the initial second spurious voltages discharging step is performed with a second discharge option different than the first discharge option; and

the repeated second spurious voltages discharging step is performed with a third discharge option different than the first and second discharge options.