Circuit and method for transforming data input/output format in parallel bit test

• US 6,909,650 B2
• Filed: 11/19/2003
• Issued: 06/21/2005
• Est. Priority Date: 11/20/2002
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Choong-sun, Ryu, Jin-ho, Chu, Yong-gyu
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/716,773
• Publication Number:
  US 20040130952A1
• Time in Patent Office: 580 Days
• Field of Search: 365/201, 365/220, 365/189.12, 365/240
• US Class Current: 365/201
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

Provided are a circuit and a method for transforming a data input/output format of a semiconductor memory device which is capable of generating various types of data patterns when the number of memory cells connected to one column selection line is greater than the number of data input pins. The circuit for transforming a data input/output format of a semiconductor memory device includes a first transmission circuit, a second transmission circuit, and a mode register set (MRS). The first transmission circuit is activated when a first test mode signal is enabled, receives n data inputs from n data input ends, and transmits the n data inputs to m memory cells. Here, n and m are natural numbers and m is greater than n. The second transmission circuit is activated when a second test mode signal is enabled, receives n data inputs from the n data input ends, and transmits the n data inputs to the m memory cells. The mode register set (MRS) receives a command and an address from outside the semiconductor device and outputs the first test mode signal and the second test mode signal according to combinations of the command and the address. In particular, data that is transmitted to adjacent memory cells of the m memory cells is inputted to different input ends of the n data input ends.

Claims

1. A circuit for transforming a data input/output format of a semiconductor memory device, the circuit comprising:

a first transmission circuit which is activated when a first test mode signal is enabled, receives n data inputs from n data input ends, and transmits the n data inputs to m memory cells, wherein n and m are natural numbers and m is greater than n; and

a second transmission circuit which is activated when a second test mode signal is enabled, receives n data inputs from the n data input ends, and transmits the n data inputs to the m memory cells,

wherein data that is transmitted to adjacent memory cells of the m memory cells is inputted to different input ends of the n data input ends.

2. The circuit of claim 1 further comprising a command register which receives a command and an address from outside the semiconductor device and outputs the first test mode signal and the second test mode signal according to combinations of the command and the address.

3. The circuit of claim 2, wherein the command register is a mode register set (MRS).

4. The circuit of claim 1, wherein the first transmission circuit comprises m switches which connect the n data input ends with the m memory cells in response to the first test mode signal.

5. The circuit of claim 1 wherein the second transmission circuit comprises m switches which connect the n data input ends with the m memory cells in response to the second test mode signal.

6. A method for transforming a data input/output format of a semiconductor memory device, the method comprising:

enabling a first test mode signal;

receiving n data inputs from n data input ends and transmitting the n data inputs to m memory cells while the first test mode signal is enabled, wherein n and m are natural numbers and m is greater than n; and

receiving n data inputs from the n data input ends and transmitting the n data inputs to the m memory cells while the second test mode signal is enabled,

wherein data that is transmitted to adjacent memory cells of the m memory cells is input to different input ends of the n data input ends.

7. The method of claim 6 further comprising receiving a command and an address from outside the semiconductor memory device and generating the first test mode signal and the second test mode signal according to combinations of the command and the address.