Contact for use in an integrated circuit and a method of manufacture therefor

• US 6,910,907 B2
• Filed: 11/18/2003
• Issued: 06/28/2005
• Est. Priority Date: 11/18/2003
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Maury, Alvaro, Layadi, Nace
• Primary Examiner(s): Prasad, Chandrika
• Application Number:
  US10/716,299
• Publication Number:
  US 20050106919A1
• Time in Patent Office: 588 Days
• Field of Search: 439/290, 439/458, 439/464, 439/691, 257/621, 257/774
• US Class Current: 439/290
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.

Claims

1. A contact for use in an integrated circuit, comprising:

a via located in a substrate; and

a contact plug located in said via, wherein said contact plug has a first portion having a notch removed therefrom and a second portion filling said notch, and wherein a geometric shape of a cross-section of said second portion is non-conformal to a geometric shape of a cross-section of said via.

2. The contact as recited in claim 1 wherein said first and second portions comprise tungsten.

3. The contact as recited in claim 1 wherein said notch has a depth ranging from about 20 nm to about 600 nm.

4. The contact as recited in claim 1 wherein an opening of said notch has an width ranging from about 50 nm to about 150 nm.

5. The contact as recited in claim 1 further including an adhesion layer located within said notch and between said first and second portions.

6. The contact as recited in claim 5 wherein said adhesion layer has a thickness ranging from about 5 nm to about 15 nm.

7. The contact as recited in claim 5 wherein said adhesion layer is a titanium/titanium nitride adhesion layer.

8. The contact as recited in claim 1 being substantially free of a seam or void.

9. A method for manufacturing a contact for use in an integrated circuit, comprising:

forming a via in a substrate; and

placing a contact plug in said via, wherein said contact plug has a first portion having a notch removed therefrom and a second portion filling said notch, and wherein a geometric shape of a cross-section of said second portion is non-conformal to a geometric shape of a cross-section of said via.

10. The method as recited in claim 9 wherein said placing includes etching said notch within said first portion and subsequently depositing said second portion within said notch.

11. The method as recited in claim 9 wherein said placing a contact plug having first and second portions include placing a contact plug having first and second tungsten portions.

12. The method as recited in claim 9 wherein said notch has a depth ranging from about 20 nm to about 600 nm.

13. The method as recited in claim 9 wherein an opening of said notch has an width ranging from about 50 nm to about 150 nm.

14. The method as recited in claim 9 further including depositing an adhesion layer within said notch and between said first portion and said second portion.

15. The method as recited in claim 14 wherein depositing an adhesion layer includes depositing an adhesion layer having a thickness ranging from about 5 nm to about 15 nm.

16. The method as recited in claim 14 wherein depositing an adhesion layer includes depositing a titanium/titanium nitride adhesion layer.

17. The method as recited in claim 9 wherein said placing includes placing a contact plug in said via being substantially free of a seam or void.

18. An integrated circuit, comprising:

transistors located over a substrate; and

an interlevel dielectric layer located over said transistors, said interlevel dielectric layer having a contact for contacting said transistors located therein, said contact including;

a via located in said interlevel dielectric layer; and

a contact plug located in said via, wherein said contact plug has a first portion having a notch removed therefrom and a second portion filling said notch, and wherein a geometric shape of a cross-section of said second portion is non-conformal to a geometric shape of a cross-section of said via.

19. The integrated circuit as recited in claim 18 further including an adhesion layer located within said notch and between said first portion and said second portion.

20. The integrated circuit as recited in claim 18 wherein said transistors are selected from the group consisting of:

CMOS devices;

BiCMOS devices; and

bipolar devices.