Apparatus and method for electromechanical testing and validation of probe cards

• US 6,911,814 B2
• Filed: 07/01/2003
• Issued: 06/28/2005
• Est. Priority Date: 07/01/2003
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Hreish, Emad B.
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US10/612,235
• Publication Number:
  US 20050017708A1
• Time in Patent Office: 728 Days
• Field of Search: 324/73.1, 324754-762, 324/158.1, 702/85, 702/89, 702/104, 702/119
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/11 using pulse reflection methods
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A method of testing a probe card includes the step of positioning the probe card in a prober over a verification wafer that is placed on a stage. The probe card is brought in contact with a contact region on the verification wafer. The verification wafer includes a shorting plane surrounding the contact region. A test signal is sent through the verification wafer to the probe card. A response signal from the probe card is received and analyzed.

Claims

1. A method of testing a probe card comprising the steps of:

positioning the probe card in a prober over a verification wafer;

bringing the probe card in contact with a contact region on the verification wafer, the verification wafer including a shorting plane surrounding the contact region;

sending a test signal through the contact region to the probe card; and

receiving a response signal from the probe card through the verification wafer.

2. The method of claim 1, further including the step of receiving the response signal over a cable attached to the verification wafer.

3. The method of claim 1, further including the step of continuously sending test signals through the verification wafer while bringing the verification wafer in contact with the probe card so as to measure height of probes on the probe card.

4. The method of claim 1, further including the step of performing a continuity test on a signal path in the probe card.

5. The method of claim 4, further including the step of using time domain reflectometry (TDR) to perform the continuity test.

6. The method of claim 4, further including the step of using frequency domain reflectometry (FDR) to perform the continuity test.

7. The method of claim 1, further including the step of determining impedance of a signal path in the probe card.

8. The method of claim 1, further including the step of testing leakage current in the probe card.

9. The method of claim 1, further including the step of measuring planarity of the probe card by bringing the probe card and the verification wafer together until probes of the probe card make contact with the verification wafer, and measuring a position of the verification wafer along a direction perpendicular to the verification wafer.

10. The method of claim 1, further including the step of verifying location of probes of the probe card.

11. The method of claim 1, further including the steps of:

bringing the probe card in contact with a plurality of contact regions on the verification wafer during the step of bringing the probe card in contact with the contact region;

sending test signals through the contact regions on the verification wafer to the probe card; and

receiving response signals from the probe card.

12. A method of testing a probe card comprising the steps of:

positioning the probe card having probes in a prober over a blank wafer;

bringing the probe card in contact with the blank wafer;

making scrub marks on the blank wafer with the probes by moving the blank wafer in an X, Y plane; and

examining the scrub marks on the blank wafer to determine location of the probes.

13. A method of testing a probe card comprising the steps of:

placing a verification wafer in a prober, the verification wafer having a contact region, a shorting plane surrounding the contact region, and an electrical connection to a tester;

positioning the probe card in the prober over the verification wafer;

bringing the probe card in contact with the contact region;

generating a test signal in the tester;

transmitting the test signal to the probe card through the contact region; and

receiving a response signal from the probe card over the electrical connection.

14. The method of claim 13, wherein the electrical connection includes a cable attached to the verification wafer.

15. The method of claim 13, further including the step of continuously sending test signals through the verification wafer while bringing the verification wafer in contact with the probe card so as to measure height of probes on the probe card.

16. The method of claim 13, further including the step of performing a continuity test on a signal path between a test signal generator and the probe card.

17. The method of claim 16, further including the step of using time domain reflectometry (TDR) to perform the continuity test.

18. The method of claim 16, further including the step of using frequency domain reflectometry (FDR) to perform the continuity test.

19. The method of claim 13, further including the step of determining impedance of a signal path between a test signal generator and the probe card.

20. The method of claim 13, further including the step of testing leakage current in the probe card.

21. The method of claim 13, further including the step of measuring planarity of the probe card by bringing the probe card and the verification wafer together until probes of the probe card make contact with the verification wafer, and measuring a position of the verification wafer along a direction perpendicular to the verification wafer.

22. The method of claim 13, further including the step of verifying location of probes of the probe card.

23. The method of claim 13, further including the steps of:

bringing the probe card in contact with a plurality of contact regions on the verification wafer during the step of bringing the probe card in contact with the contact region;

sending test signals through the contact regions to the probe card; and

receiving response signals from the probe card.

24. A system for testing a probe card comprising:

a prober including means for moving a verification wafer in at least a vertical direction;

a verification wafer positioned on means for moving and having a contact region surrounded by a shorting plane;

an electrical connection from the contact region to a test signal generator,

wherein signals generated by the test signal generator are transmitted to a probe on a probe card under test.

25. The system of claim 24, wherein the verification wafer includes a plurality of contact regions surrounded by the shorting plane for testing multiple probes on the probe card under test.

26. The system of claim 24, wherein the electrical connection is one of a coaxial cable and a flex cable.

27. The system of claim 24, wherein the test generator includes a time domain reflectometry apparatus.

28. The system of claim 24, wherein the test generator includes a frequency domain reflectometry apparatus.