Delay matching for clock distribution in a logic circuit

• US 6,911,856 B2
• Filed: 07/31/2003
• Issued: 06/28/2005
• Est. Priority Date: 07/31/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Florescu, Octavian
• Primary Examiner(s): NGUYEN, LINH M
• Application Number:
  US10/632,651
• Publication Number:
  US 20050024116A1
• Time in Patent Office: 698 Days
• Field of Search: 327/202, 327/217, 327/250, 327/251, 327/407, 327/408
• US Class Current: 327/250
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

Claims

1. A clock distribution circuit comprising:

a clock source to generate a clock signal;

a clock divider to divide the clock signal and produce a divided clock signal, and including a flip-flop that introduces a first propagation delay to the divided clock signal; and

a delay matching circuit to distribute the clock signal, and to introduce a second propagation delay to the clock signal, the second propagation delay substantially matching the first propagation delay introduced in the divided clock signal by the flip-flop, wherein the delay matching circuit includes;

a multiplexer having a first input coupled to drive a first transmission gate, a second input coupled to drive a second transmission gate, a select input coupled to the clock source to selectively enable one of the transmission gates, and an output coupled to the first and second transmission gates, wherein the transmission gates are configured to correspond substantially to a slave transmission gate in the flip-flop;

a PMOS transistor having a drain coupled to the first input, a gate coupled to ground, and a source coupled to a supply voltage, wherein the PMOS transistor is configured to correspond substantially to a PMOS transistor in a master output driver of the flip-flop; and

an NMOS transistor having a drain coupled to the second input, a gate coupled to the supply voltage, and a source coupled to ground, wherein the NMOS transistor is configured to correspond substantially to an NMOS transistor in the master output driver of the flip-flop.

2. The circuit of claim 1, wherein the PMOS transistor is configured to correspond substantially in size to the PMOS transistor in the master output driver of the flip-flop, and the NMOS transistor is configured to correspond substantially in size to the NMOS transistor in the master output driver of the flip-flop.

3. A delay matching circuit comprising:

multiplexer coupled to a clock source;

transmission gates within the multiplexer to substantially mimic characteristics of a slave transmission gate in a flip-flop;

inputs coupled to the multiplexer to substantially mimic characteristics of a master output driver of the flip-flop;

an output coupled to the multiplexer to substantially mimic characteristics of an output driver in the flip flop; and

a PMOS transistor having a drain coupled to a first one of the inputs, a gate coupled to ground, and a source coupled to a supply voltage, wherein the PMOS transistor is configured to correspond substantially to a PMOS transistor in a master output driver of the flip-flop; and

an NMOS transistor having a drain coupled to a second one of the inputs, gate coupled to the supply voltage, and a source coupled to ground, wherein the NMOS transistor is configured to correspond substantially to an NMOS transistor in the master output driver of the flip-flop.

4. A delay matching circuit comprising:

a multiplexer having a first input coupled to drive a first transmission gate, a second input coupled to drive a second transmission gate, a select input coupled to a clock source to selectively enable one of the transmission gates, and an output coupled to the first and second transmission gates, wherein the transmission gates are configured to correspond substantially to a slave transmission gate in a flip-flop;

a PMOS transistor having a drain coupled to the first input, a gate coupled to ground, and a source coupled to a supply voltage, wherein the PMOS transistor is configured to correspond substantially to a PMOS transistor in a master output driver of the flip-flop;

an NMOS transistor having a drain coupled to the second input, a gate coupled to the supply voltage, and a source coupled to ground, wherein the NMOS transistor is configured to correspond substantially to an NMOS transistor in the master output driver of the flip-flop; and

an inverter coupled to the output of the multiplexer, wherein the inverter is configured to correspond substantially to an output driver in the flip flop.

5. A circuit comprising:

a signal source to generate a signal;

a signal distribution circuit to modify the signal and distribute a modified signal, and including a flip-flop that introduces a first propagation delay in the modified signal; and

a delay matching circuit to distribute the signal, and introduce a second propagation delay to the signal, the second propagation delay substantially matching the first propagation delay introduced in the modified signal by the flip-flop,

wherein the delay watching circuit includes a multiplexer having a first input coupled to drive a first transmission gate, a second input coupled to drive a second transmission gate, a select input coupled to the signal source to selectively enable one of the transmission gates, and an output coupled to the first and second transmission gates, wherein the transmission gates are configured to correspond substantially to a slave transmission gate in the flip-flop, wherein the delay marching circuit further includes;

a PMOS transistor having a drain coupled to the first input, a gate coupled to ground, and a source coupled to a supply voltage, wherein the PMOS transistor is configured to correspond substantially to a PMOS transistor in a master output driver of the flip-flop; and

an NMOS transistor having a drain coupled to the second input, a gate coupled to the supply voltage, and a source coupled to ground, wherein the NMOS transistor is configured to correspond substantially to an NMOS transistor in the master output driver of the flip-flop.

6. The circuit of claim 5, wherein the PMOS transistor is configured to correspond substantially in size to the PMOS transistor in the master output driver of the flip-flop, and the NMOS transistor to configured to correspond substantially in size to the NMOS transistor in the master output driver of the flip-flop.

7. A method comprising:

dividing a clock signal with a flip-flop to produce a divided clock signal, and to introduce a propagation delay to the divided clock signal; and

introducing a second propagation delay to the clock signal with a delay marching circuit, the second propagation delay substantially marching the first propagation delay introduced in the divided clock signal by the flip-flop, wherein the delay matching circuit substantially mimics delay characteristics of the flip-flop,

wherein the delay matching circuit includes a multiplexer having a first input coupled to drive a first transmission gate, a second input coupled to drive a second transmission gate, a select input coupled to the clock source to selectively enable one of the transmission gates, and an output coupled to the first and second transmission gates, and wherein the transmission gates are configured to correspond substantially to slave transmission gates in the flip-flop, wherein the delay matching circuit includes;

a PMOS transistor having a drain coupled to the first input, a gate coupled to ground, and a source coupled to a supply voltage, wherein the PMOS transistor is configured to correspond substantially to a PMOS transistor in a master output driver of the flip-flop; and

an NMOS transistor having a drain coupled to the second input, a gate coupled to the supply voltage, and a source coupled to ground, wherein the NMOS transistor is configured to correspond substantially to an NMOS transistor in the master output driver of the flip-flop.