Frame buffer pixel circuit for liquid crystal display

• US 6,911,964 B2
• Filed: 11/07/2002
• Issued: 06/28/2005
• Est. Priority Date: 11/07/2002
• Status: Expired due to Fees

• Current Assignee: Duke University, Ge Betz
• Original Assignee: Duke University
• Inventors: Lee, Sangrok, Morizio, James C., Johnson, Kristina M.
• Primary Examiner(s): CHOW, DOON Y
• Application Number:
  US10/289,459
• Publication Number:
  US 20040090411A1
• Time in Patent Office: 964 Days
• Field of Search: 345 87-104, 345204-214, 345695-699, 349/41, 349/42, 349/49, 349/50, 349/51
• US Class Current: 345/90
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An enhanced frame buffer pixel circuit with two control transistors and a separate capacitor put in as a memory capacitor before the memory transistor yields a high contrast ratio by removing induced charge and solving a charge sharing problem between the memory capacitor and the liquid crystal display (LCD) capacitor. The memory transistor may be made of either CMOS or PMOS. The frame buffer pixel can be used to drive binary displays which expresses ON and OFF only if a comparator is put in after the pixel electrode circuit to represent gray levels with reduced sub-frame frequency.

Claims

1. An analog frame buffer pixel system, comprising:

a first storage unit for storing first analog data;

a first controller for enabling storage of the first analog data in the first storage unit;

a second storage unit for storing a second analog data proportional to the first analog data and corresponding to a grayscale pixel value to be displayed;

a display for displaying the pixel value corresponding to the second analog data stored in the second storage unit;

a second controller to enable storage of the second analog data into the second storage unit;

a drain unit for draining voltage from the second storage unit after the pixel value is displayed, wherein the first storage unit includes a transistor having a first terminal for storing the first analog data, a second terminal coupled to a supply potential, and a third terminal coupled to the second storage unit, said first terminal coupled to the first controller and corresponding to a gate of the transistor; and

a capacitor coupled between the fist terminal of the transistor and a reference potential.

2. The system according to claim 1, wherein the first controller includes a pass gate which, when turned off, causes the first analog data to be stored at the gate of the transistor.

3. The system according to claim 2, wherein the pass gate includes at least one of an NMOS transistor and a PMOS transistor.

4. The system according to claim 2, wherein the the pass gate includes NMOS transistor and PMOS transistor which are controlled by Write and Inverted Write signals respectively.

5. The system according to claim 1, wherein the second controller comprises a transistor having a gate coupled to a Read signal.

6. The system according to claim 1, wherein the display comprises a pixel electrode and a capacitor, the capacitor being independently optimized to hold a charge corresponding to the pixel value for one frame time.

7. The system according to claim 1, wherein the drain unit comprises a transistor having a gate connected to a Pulldown signal.

8. The system according to claim 1, wherein the display is a liquid crystal display.

9. The system according to claim 1, further comprising:

a power source coupled to the second storage unit which includes a capacitor,

wherein the second controller allows the power source to charge the capacitor of the second storage unit to a value which corresponds to the second analog data, the second controller allowing the power source to charge the capacitor of the second storage unit through the first storage unit based on the first analog value.

10. An analog frame buffer pixel system, comprising:

a first storage unit for storing first analog data;

a first controller for enabling storage of the first analog data;

a second storage unit for storing a second analog data proportional to the first analog data;

a display for displaying a pixel value based on the second analog data stored in the second storage unit;

a second controller to enable storage of the second analog data into the second storage unit to the display;

a drain unit for draining voltage from the second storage unit after the pixel value is displayed; and

an analog to pulse width modulation (PWM) converter coupled between an output of the second storage unit and an input of a pixel electrode, wherein the first storage unit includes;

a transistor having a first terminal coupled to the first controller, a second terminal coupled to a supply potential, and a third terminal coupled to the second storage unit, said first terminal corresponding to a gate of the transistor, and

a capacitor coupled to a node disposed between the gate of the transistor and the first controller.

11. The system according to claim 10, wherein the capacitor has a capacitance independent from the first data stored in the capacitor, and wherein the first controller includes a pass gate.

12. The system according to claim 11, wherein the capacitor comprises a complementary metal oxide semiconductor (CMOS) having double POLY layers.

13. The system according to claim 11, wherein the pass gate includes at least one of an NMOS transistor and a PMOS transistor.

14. The system according to claim 11, wherein the pass gate includes an NMOS transistor and a PMOS transistor controlled by Write and Inverted Write signals respectively.

15. The system according to claim 10, wherein the second controller comprises a transistor having a gate coupled to a Read signal.

16. The system according to claim 10, wherein the display comprises a pixel electrode and a capacitor, the capacitor being independently optimized to hold a charge corresponding to the pixel value for one frame time.

17. The system according to claim 10, wherein the drain unit comprises a transistor having a gate connected to a Pulldown signal.

18. The system according to claim 10, wherein the converter comprises a comparator which compares the second analog data to a reference value and outputs a binary value corresponding to said pixel value.

19. The system according to claim 18, wherein the reference voltage swings within a voltage range generated from the frame buffer pixel.

20. The system according to claim 10, further comprising:

a power source coupled to the second storage unit which includes a capacitor,

wherein the second controller allows the power source to charge the capacitor of the second storage unit to a value which corresponds to the second analog data, the second controller allowing the power source to charge the capacitor of the second storage unit through the first storage unit based on the first analog value.

21. A frame buffer pixel circuit for a display system, comprising:

a first storage unit which stores first analog data;

a second storage unit which stores second analog data proportional to the first analog data in the first storage unit;

a controller which couples the first storage unit to the second storage unit to enable storage of the second analog data in the second storage unit; and

a pixel electrode for displaying a pixel value corresponding to the second analog data stored in the second storage unit, wherein the first storage unit includes a transistor having a first terminal for storing the first analog data, a second terminal coupled to a supply potential, and a third terminal coupled to the second storage unit, said first terminal corresponding to a gate of the transistor; and

a capacitor coupled between the fist terminal of the transistor and a reference potential.

22. The circuit according to claim 21, further comprising:

a power source coupled to the second storage unit which includes a capacitor, wherein the controller allows the power source to charge the capacitor of the second storage unit to a value which corresponds to the second analog data based on the first analog value.