Higher and lower definition patterning of an active plate

• US 6,912,037 B2
• Filed: 05/20/2002
• Issued: 06/28/2005
• Est. Priority Date: 05/23/2001
• Status: Expired due to Fees

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Deane, Steven C.
• Primary Examiner(s): Schechter, Andrew
• Application Number:
  US10/151,085
• Publication Number:
  US 20020176031A1
• Time in Patent Office: 1,135 Days
• Field of Search: 349/39, 349/46, 349/141, 349/187
• US Class Current: 349/187
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

The storage capacitor of an active matrix liquid crystal display is formed to have a second electrode (28) that laterally overlaps a first electrode (10). The drain (30) of a thin film transistor extends across the gate electrode (2). The gate electrode (2) and the first electrode (10) of the storage capacitor are formed from a single metallization layer. The width of the gate electrode (2) and the first electrode (10) will tend to vary in parallel, as a result of process variation. This parallel variation tends to cancel out subsequent variation in the kick back voltage.

Claims

1. An active plate comprising:

a substrate;

a first metallization layer defining gate electrodes and further defining first storage capacitor electrodes extending longitudinally across the substrate, thereby forming corresponding lateral edges of the first storage capacitor electrodes;

a second metallization layer defining source and drain electrodes and second storage capacitor electrodes;

a semiconductor body layer forming thin film transistor bodies between the source and drain electrodes; and

an insulation layer between first and second storage capacitor electrodes,

thereby forming a plurality of pixel elements, each pixel element having a corresponding source, drain, and gate electrode, and a corresponding first and second storage capacitor electrode;

wherein

the drain electrode extends completely across at least one dimension of the gate electrode, and the second storage capacitor electrode overlaps the lateral edges of the first storage capacitor electrode, and

the second storage capacitor electrode includes a plurality of elements having a width within a factor of 2 of a width of the drain electrode.

2. The active plate of claim 1 wherein the plurality of elements extend laterally across the first storage capacitor electrode.

3. The active plate of claim 2 wherein the second storage capacitor electrode includes a plurality of elements extending laterally across a width of the first capacitor electrode and connected together by at least one longitudinal element.

4. A method of manufacture of an active plate, comprising:

depositing and patterning using a lower definition patterning process a first metallization layer on a substrate, the first metallization layer defining gate electrodes and first storage capacitor electrodes extending longitudinally across the substrate, and having corresponding lateral edges extending longitudinally across the substrate;

depositing an insulation layer;

depositing and patterning using a lower definition patterning process a semiconductor body layer forming thin film transistor bodies; and

depositing and patterning using a higher definition process a second metallization layer defining source and drain electrodes and second storage capacitor electrodes,

such that the second storage capacitor electrodes overlap the lateral edges of the first storage capacitor electrode.

5. The method of claim 4 performed such that

the drain electrode extends across at least one dimension of the gate electrode.

6. The method of claim 4 performed such that

the higher definition process is photolithography and the lower definition process is printing.

7. A method of manufacture or an active plate, comprising:

depositing and patterning a first metallization layer on a substrate using a lower definition patterning process,

the first metallization layer defining gate electrodes and first storage capacitor electrodes extending longitudinally across the substrate, and having corresponding lateral edges extending longitudinally across the substrate;

depositing an insulation layer;

depositing and patterning a semiconductor body layer forming thin film transistor bodies; and

depositing and patterning a second metallization layer defining source and drain electrodes and second storage capacitor electrodes using a higher definition patterning process,

such that the second storage capacitor electrodes overlap the lateral edges of the first storage capacitor electrode.

8. The method of claim 7, performed such that

the drain electrode extends across at least one dimension of the gate electrode.

9. The method of claim 7, performed such that

the higher definition process is photolithography and

the lower definition process for depositing and patterning the first metallization process includes printing.

10. The method of claim 7, performed such that

the lower definition process for depositing and patterning the semiconductor body layer includes printing.

11. An active plate, comprising:

a substrate;

a first metallization layer defining gate electrodes and further defining first storage capacitor electrodes extending longitudinally across the substrate, thereby forming corresponding lateral edges of the first storage capacitor electrodes;

a second metallization layer defining source and drain electrodes and second storage capacitor electrodes;

a semiconductor body layer forming thin film transistor bodies between the source and drain electrodes; and

an insulation layer between first and second storage capacitor electrodes,

such that the first and second metallization layers, the semiconductor body, and the insulation layer are arranged to form a plurality of pixel elements, each pixel element having a corresponding source, drain, and gate electrode, and a corresponding first and second storage capacitor electrode;

wherein

thin first metallization layer exhibits a first variance of width longitudinally across the substrate that is substantially greater than a second variance of width of the second metallization layer longitudinally across the substrate, and

the drain electrode extends completely across at least one dimension of the gate electrode, and the second storage capacitor electrode overlaps the lateral edges of the first storage capacitor electrode.

12. The active plate of claim 11, wherein a width of the gate electrode corresponding to the at least one dimension is from 0.8 to 1.2 times a width of the first storage capacitor electrode.

13. The active plate of claim 11, wherein the semiconductor body extends longitudinally over the gate electrode.

14. A liquid crystal display comprising:

an active plate,

a passive plate and

liquid crystal between the active and passive plates,

the active plate comprising;

a substrate;

a first metallization layer defining gate electrodes and further defining first storage capacitor electrodes extending longitudinally across the substrate;

a second metallization layer defining source and drain electrodes and second storage capacitor electrodes;

a semiconductor body layer forming thin film transistor bodies between the source and drain electrodes; and

an insulation layer between first and second storage capacitor electrodes,

wherein

the first metallization layer exhibits a first variance of width longitudinally across the substrate that is substantially greater than a second variance of width of the second metallization layer longitudinally across the substrate, and

each drain electrode extends completely across at least one dimension of each gate electrode, and each second storage capacitor electrode overlaps the lateral edges of each first storage capacitor electrode.

15. An active plate produced by

depositing and patterning a first metallization layer on a substrate using a lower definition patterning process.

the first metallization layer defining gate electrodes and first storage capacitor electrodes extending longitudinally across the substrate, and having corresponding lateral edges extending longitudinally across the substrate;

depositing an insulation layer;

depositing and patterning a semiconductor body layer forming thin film transistor bodies; and

depositing and patterning a second metallization layer defining source and drain electrodes and second storage capacitor electrodes using a higher definition patterning process, so that a variance of a width of the second metallization layer longitudinally across the surface is substantially less than a variance of a width of the first metallization layer longitudinally across the surface,

wherein

the second storage capacitor electrodes overlap the lateral edges of the first storage capacitor electrode.

16. The active plate of claim 15, wherein the second storage capacitor electrode includes a plurality of elements having a width with in a factor of 2 of a width of the drain electrode.

17. The active plate of claim 15, wherein a width of the gate electrode is from 0.8 to 1.2 times a width of the first storage capacitor electrode.

18. The active plate of claim 15, wherein the semiconductor body extends longitudinally over the gate electrode.