Method and system for fast memory access

• US 6,912,173 B2
• Filed: 06/25/2002
• Issued: 06/28/2005
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Beat, Robert
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/178,270
• Publication Number:
  US 20030002376A1
• Time in Patent Office: 1,099 Days
• Field of Search: 365/230.03, 365/230.04, 365/230.06, 365/230.08, 365/189.04, 365/233, 365/189.05, 365/189.12
• US Class Current: 365/230.03
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.

Claims

1. A memory system that can access a misaligned data word, comprising:

a first memory section coupled to a first address bus;

a second memory section coupled to a second address bus,

an address device that simultaneously provides a first address to the first memory section using the first address bus and a second address to the second memory section using the second address bus, wherein the second address is not equal to the first address; and

buffer circuitry that performs an access operation for the misaligned data word,

wherein the access operation is at least one of a simultaneous read operation to the first and second memory sections or a simultaneous write operation to the first and second memory sections,

wherein the buffer circuitry reads a first portion of the misaligned data word from the first memory section and reads a second portion of the misaligned data word from the second memory section.

2. The system of claim 1, wherein the buffer circuitry receives the first and second word portions and assembles the word from the first and second word portions.

3. A memory system that can access a misaligned data word, comprising:

a first memory section coupled to a first address bus;

a second memory section coupled to a second address bus,

an address device that simultaneously provides a first address to the first memory section using the first address bus and a second address to the second memory section using the second address bus, wherein the second address is not equal to the first address; and

buffer circuitry that performs an access operation for the misaligned data word,

wherein the access operation is at least one of a simultaneous read operation to the first and second memory sections or a simultaneous write operation to the first and second memory sections,

wherein the buffer circuitry writes a first portion of the misaligned data word to the first memory section and writes a second portion of the misaligned data word to the second memory section.

4. The system of claim 3, wherein the buffer circuitry effectively performs a shift operation on the word before the buffer circuitry performs the write operations.

12. The system of claim 3, wherein the address device further provides write control information signals to a plurality of first modules of the first memory section, wherein the write control information signals activate write operations on only those first modules designated for data word information.

5. A memory system that can access a misaligned data word, comprising:

a first memory section coupled to a first address bus;

a second memory section coupled to a second address bus,

an address device that simultaneously provides a first address to the first memory section using the first address bus and a second address to the second memory section using the second address bus, wherein the second address is not equal to the first address; and

buffer circuitry that performs an access operation for the misaligned data word,

wherein the access operation is at least one of a simultaneous read operation to the first and second memory sections or a simultaneous write operation to the first and second memory sections,

wherein the access operation is performed in a single cycle and

wherein the first memory section contains a same number of bits as the second memory section.

6. A memory system that can access a misaligned data word, comprising:

a first memory section coupled to a first address bus;

a second memory section coupled to a second address bus,

an address device that simultaneously provides a first address to the first memory section using the first address bus and a second address to the second memory section using the second address bus, wherein the second address is not equal to the first address; and

buffer circuitry that performs an access operation for the misaligned data word,

wherein the access operation is at least one of a simultaneous read operation to the first and second memory sections or a simultaneous write operation to the first and second memory sections,

wherein the access operation is performed in a single cycle and

wherein the second address is one location higher than the first memory location.

7. The system of claim 6, wherein the first and second address busses have at least one disjoint address line.

8. The system of claim 6, wherein the first and second address busses have at least a plurality of disjoint address lines.

9. The system of claim 8, wherein the address lines of the first and second address busses are completely disjoint.

10. A memory system that can access a misaligned data word, comprising:

a first memory section coupled to a first address bus;

a second memory section coupled to a second address bus,

an address device that simultaneously provides a first address to the first memory section using the first address bus and a second address to the second memory section using the second address bus, wherein the second address is not equal to the first address; and

buffer circuitry that performs an access operation for the misaligned data word,

wherein the access operation is at least one of a simultaneous read operation to the first and second memory sections or a simultaneous write operation to the first and second memory sections,

wherein the access operation is performed in a single cycle and

wherein the address device further provides a plurality of read control information signals to a plurality of first modules of the first memory section,

wherein the read control information signal activates read operations on only those first modules containing word data.

11. The system of claim 10, wherein the address device further provides a plurality of write control information signals to the plurality of first modules of the first memory section, wherein the write control information signals activate write operations on only those first modules designated for data word information.

13. A memory system that can access a misaligned data word held in first and second separately addressable memory sections, comprising:

a first memory section for holding a first portion of the misaligned data word at a first location;

a second memory section for holding a second portion of the misaligned data word at a second location;

an addressing means that simultaneously provides a first address to the first memory section and a second address to the second memory section, the first and second memory addresses respectively indicating the locations of first and second portions of the misaligned data word in the first and second memory sections; and

a buffering means that performs an access operation in a single memory-access cycle, wherein the access operation is at least one of a simultaneous read operation from the first and second memory sections or a simultaneous write operation to the first and second memory sections,

wherein the first memory section is an array comprising even address locations and the second memory section is a different memory array comprising odd address locations.