Integrated optical/electronic circuits and associated methods of simultaneous generation thereof

• US 6,912,330 B2
• Filed: 11/10/2001
• Issued: 06/28/2005
• Est. Priority Date: 05/17/2001
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Sioptical Inc. (Cisco Systems, Inc.)
• Inventors: Deliwala, Shrenik
• Primary Examiner(s): ULLAH, AKM E
• Application Number:
  US09/991,542
• Publication Number:
  US 20030039430A1
• Time in Patent Office: 1,326 Days
• Field of Search: 385/24, 385/15, 385/16, 385/10, 385/18, 385/47, 385/2, 385/8, 385/37, 437/209.2, 372/102, 372/103, 372/64, 372/85, 372/99, 372/43, 372/45
• US Class Current: 385/14
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: G02B 2006/12038 Glass (SiO2 based materials)
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12097 Ridge, rib or the like
• CPC Class Codes: G02B 2006/12104 Mirror; Reflectors or the like
• CPC Class Codes: G02B 2006/12107 Grating
• CPC Class Codes: G02B 2006/12114 Prism
• CPC Class Codes: G02B 2006/12135 Temperature control
• CPC Class Codes: G02B 2006/12161 Distributed feedback [DFB]
• CPC Class Codes: G02B 2006/12164 Multiplexing; Demultiplexing
• CPC Class Codes: G02B 2006/12176 Etching
• CPC Class Codes: G02B 27/285 comprising arrays of elements, e.g. microprisms
• CPC Class Codes: G02B 5/045 Prism arrays
• CPC Class Codes: G02B 6/10 of the optical waveguide type G02B6/02, G02B6/24 take precedence; devices or arrangements for the control of light by electric, magnetic, electro-magnetic or acoustic means G02F1/00; transferring the modulation of modulated light G02F2/00; optical logic elements G02F3/00; optical analogue/digital converters G02F7/00
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/12007 forming wavelength selective elements, e.g. multiplexer, demultiplexer
• CPC Class Codes: G02B 6/12011 characterised by the arrayed waveguides, e.g. comprising a filled groove in the array section
• CPC Class Codes: G02B 6/12026 characterised by means for reducing the temperature dependence
• CPC Class Codes: G02B 6/12033 characterised by means for configuring the device, e.g. moveable element for wavelength tuning switching G02B6/35; thermo-optic devices G02F1/0147
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02B 6/1228 : Tapered waveguides, e.g. integrated spot-size transformers for coupling with fibres G02B6/305
• CPC Class Codes: G02B 6/124 : Geodesic lenses or integrated gratings
• CPC Class Codes: G02B 6/2861 : using fibre optic delay lines and optical elements associated with them, e.g. for use in signal processing, e.g. filtering delay lines in general H03H, H01P9/00; optical computing devices G06E
• CPC Class Codes: G02B 6/29349 : Michelson or Michelson/Gires-Tournois configuration, i.e. based on splitting and interferometrically combining relatively delayed signals at a single beamsplitter
• CPC Class Codes: G02B 6/29358 : Multiple beam interferometer external to a light guide, e.g. Fabry-Pérot, etalon, VIPA plate, OTDL plate, continuous interferometer, parallel plate resonator G02B6/29347, G02B6/29349, G02B6/2935, G02B6/29361 take precedence; resonator evanescently coupled to light guide G02B6/29335
• CPC Class Codes: G02B 6/34 : utilising prism or grating G02B6/293 takes precedence
• CPC Class Codes: G02B 6/4215 : the intermediate optical elements being wavelength selective optical elements, e.g. variable wavelength optical modules or wavelength lockers G02B6/4246 takes precedence
• CPC Class Codes: G02B 6/4232 : using the surface tension of fluid solder to align the elements, e.g. solder bump techniques flip-chip mounting techniques in assembly of semiconductor devices H01L24/81
• CPC Class Codes: G02B 6/43 : Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: G02F 1/0147 : based on thermo-optic effects G02F1/132 takes precedence
• CPC Class Codes: G02F 1/0152 : using free carrier effects, e.g. plasma effect
• CPC Class Codes: G02F 1/025 : in an optical waveguide structure G02F1/017, G02F1/2257 take precedence
• CPC Class Codes: G02F 1/295 : Analog deflection from or in an optical waveguide structure]
• CPC Class Codes: G02F 2201/20 : delay line
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOT waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.

Claims

1. A method for forming a hybrid active electronic and optical circuit using a lithography mask, the hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device, both devices disposed at least in part in a single Silicon-On-Insulator (SOI) wafer, the SOI wafer including an insulator layer and an upper silicon layer, the upper silicon layer including at least one component of the active electronic device and at least one component of the optical device, the method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.

2. The method of claim 1, wherein altering an electric voltage level applied to the active electronic device effects the free carrier distribution in a region of the optical device, and thereby changes the effective mode index of the region of the optical device.

3. The method of claim 1, wherein the optical device is an active optical device includes an active optical device.

4. The method of claim 1, wherein the optical device is includes a passive optical device.

5. The method of claim 1, wherein the optical device is a focusing mirror.

6. The method of claim 1, wherein the optical device is an input/output coupler that couples light into a waveguide.

7. The method of claim 1, wherein the optical device is a Fabry-Perot cavity.

8. The method of claim 1, wherein the optical device is a wavelength division multiplexer modulator.

9. The method of claim 1, wherein the optical device is an evanescent coupler.

10. The method of claim 1, wherein the optical device is a diode.

11. The method of claim 1, wherein the optical device is a transistor.

12. The method of claim 1, further comprising etching portions of the hybrid active electronic and optical circuit from a surface of the SOI wafer utilizing the lithography mask.

13. The method of claim 1, further comprising depositing materials on portions of the hybrid active electronic and optical circuit to form a surface of the SOI wafer utilizing the lithography mask.

14. The method of claim 1, wherein the optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP, and a MOSFET.

15. A method for forming a hybrid active electronic and optical circuit using a lithography mask, the hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device, both devices disposed at least in part in a single wafer, the wafer including an insulator layer and an upper silicon layer, the upper silicon layer including at least one component of the active electronic device and at least one component of the optical device, the method comprising projecting the lithography mask onto the wafer in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the wafer.

16. The method of claim 15, wherein the wafer is a silicon-on-sapphire wafer.