Math coprocessor

• US 6,912,557 B1
• Filed: 06/09/2000
• Issued: 06/28/2005
• Est. Priority Date: 06/09/2000
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Ganeshan, Murli, North, Gregory Allen
• Primary Examiner(s): NGO, CHUONG D
• Application Number:
  US09/591,659
• Time in Patent Office: 1,845 Days
• Field of Search: 708/490, 708/495, 708/520, 708/523, 708/524, 708/501, 708/503, 708/603, 708620-632, 708/518
• US Class Current: 708/490
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adder 1604 selectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier array 1603 and data output from adder 1604.

Claims

1. A digital signal processor comprising:

a multiplier-accumulator for performing integer and floating point multiplication and integer addition operations on operands selectively fetched into a set of source registers;

a floating point adder for performing floating point addition operations on operands selectively fetched into the set of source registers; and

a comparator for comparing floating point operands selectively fetched into the set of source registers.

2. The digital processor of claim 1 wherein said multiplier-accumulator comprises:

a multiplier array for selectively multiplying floating point mantissas and integers;

a fixed point adder for selectively performing addition operations on data including integers received from the set of source registers and products generated by the multiplier array; and

an accumulator including a register for accumulating result generated by the fixed point adder.

3. The digital signal processor of claim 2 wherein said multiplier-accumulator further comprises a shift register for selectively shifting data including operands received from the set of source register and results generated by the fixed point adder.

4. The digital signal processor of claim 2 wherein said digital signal processor comprises a math coprocessor in conjunction with a microprocessor.

5. The digital signal processor of claim 2 wherein said digital signal processor comprises a coprocessor operating in conjunction with a reduced Instruction set computer.

6. The digital signal processor of claim 2 wherein said multiplier-accumulator further comprises circuitry for selectively forwarding results directly to said floating point adder to prevent pipeline bubbles.

7. The digital signal processor of claim 2 wherein said floating point adder comprises circuitry for selectively forwarding results directly to said multiplier-accumulator to prevent pipeline bubbles.

8. The digital signal processor of claim 2 wherein said multiplier-accumulator comprises:

a multiplier array for multiplying first and second operands during a first clock period;

a fix point adder for adding a result from said multiplier array with a third operand during a second clock period; and

an accumulator register for storing a sum output from said adder during the second clock period.