Disk array storage subsystem with parity assist circuit that uses scatter-gather list
First Claim
1. A parity assist circuit for use with a controller, comprising:
- a scatter-gather list processor adapted for coupling to a cache memory of the controller to process a scatter-gather list each entry of which specifies parameters of at least one XOR computation to be performed; and
an XOR engine coupled to said scatter-gather list processor that produces an XOR product of data stored in the cache memory in accordance with parameters supplied by said scatter-gather list processors, wherein the parity assist circuit is operable in accordance with parameters supplied by said scatter-gather list processor to read data previously stored in the cache memory by operation of the counter, and wherein the parity assist circuit is operable to read the data to compute the XOR product without transferring the read data to a device external to the controller, and wherein the parity assist circuit is configurable to generate a single interrupt applied to a CPU of the controller regardless of the number of XOR products computer by its operation.
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Accused Products
Abstract
A parity assist circuit that provides multiple XOR calculations using a scatter-gather list is disclosed. The parity assist circuit includes a control circuit that obtains a plurality of source operands in response to a scatter-gather list, and an XOR engine that provides a plurality of XOR products computed from the supplied source operands. Destination and length parameters in the scatter-gather list are used by the XOR engine to store the XOR computation product and to determine the length of the data in the source and destination blocks to be computed. Preferably, the parity assist circuit is part of a RAID controller that includes a processor and a cache memory. The parity assist circuit preferably utilizes the scatter-gather list to gather required source operands from a memory and to scatter multiple XOR products to the memory before sending an interrupt to the processor or receiving additional setup instructions from the processor, thereby providing rapid and efficient parity calculations and improving overall system performance of the RAID storage subsystem.
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Citations
34 Claims
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1. A parity assist circuit for use with a controller, comprising:
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a scatter-gather list processor adapted for coupling to a cache memory of the controller to process a scatter-gather list each entry of which specifies parameters of at least one XOR computation to be performed; and
an XOR engine coupled to said scatter-gather list processor that produces an XOR product of data stored in the cache memory in accordance with parameters supplied by said scatter-gather list processors, wherein the parity assist circuit is operable in accordance with parameters supplied by said scatter-gather list processor to read data previously stored in the cache memory by operation of the counter, and wherein the parity assist circuit is operable to read the data to compute the XOR product without transferring the read data to a device external to the controller, and wherein the parity assist circuit is configurable to generate a single interrupt applied to a CPU of the controller regardless of the number of XOR products computer by its operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A disk array storage system including:
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a controller for controlling said disk array system; and
multiple disk drives coupled to said controller for storing data on behalf of a host computer, wherein said controller includes;
a processor;
a cache memory for storing data; and
a parity assist circuit, wherein said parity assist circuit includes;
a scatter-gather list processor to process a scatter-gather list each entry of which specifies parameters of at least one XOR computation to be performed on a portion of the data; and
an XOR engine coupled to said scatter-gather list processor that produces an XOR product in accordance with parameters supplied by said scatter-gather list processor, wherein the parity assist circuit is operable in accordance with parameters supplied by said scatter-gather list processor to read data previously stored in the cache memory by operation of the controller, and wherein the parity assist circuit is operable to read the data to compute an XOR product without transferring the read data to a device external to the controller, and wherein the parity assist circuit is configurable to generate a single interrupt applied to the processor regardless of the number of XOR products computed by its operation. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A parity assist circuit for use with a controller comprising:
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an XOR engine for computing XOR parity values using data stored in a cache memory of the controller in accordance with parameters applied to the XOR engine;
scatter-gather means for processing a scatter-gather list having at least one entry to provide said parameters to said XOR engine; and
control means for sequencing through all entries of said scatter-gather list to compute XOR parity values for corresponding to all entries in said scatter-gather list, wherein the parity assist circuit is operable in accordance with parameters supplied by said scatter-gather means to read data previously stored in the cache memory by operation of the controller, and wherein the parity assist circuit is operable to read the data to computer an XOR parity value without transferring the read data to a device external to the controller, and wherein the parity assist circuit is configurable to generate a single interrupt applied to a CPU of the controller regardless of the number of XOR parity values computed by operation of the parity assist circuit. - View Dependent Claims (27, 28, 29)
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30. A method operable within a parity assist circuit of a storage controller for computing parity values comprising the steps of:
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storing data in a cache memory of the storage controller;
providing a scatter-gather list to said parity assist circuit wherein said scatter-gather list has at least one entry defining a desired XOR computation of a portion of the data;
sequencing through each of said entries in said scatter-gather list to perform a sequence of desired XOR computations defined by the entries of said scatter-gather list wherein the parity assist circuit is operable during sequencing to read the data stored in the cache memory to compute an XOR parity sum without transferring the read data to a device external to the controller; and
generating as few as a single interrupt applied to a processor associated with the controller regardless of the number of XOR computations defined by entries of said scatter-gather list. - View Dependent Claims (31, 32, 33, 34)
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Specification