Disk array storage subsystem with parity assist circuit that uses scatter-gather list

• US 6,912,687 B1
• Filed: 05/11/2000
• Issued: 06/28/2005
• Est. Priority Date: 05/11/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Gates, Dennis, DeKoning, Rodney A.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US09/568,996
• Time in Patent Office: 1,874 Days
• Field of Search: 714/6, 714/800, 714/801, 714/805, 711/114
• US Class Current: 714/800
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 2211/1009 Cache, i.e. caches used in RAID system with parity
• CPC Class Codes: G06F 2211/1054 Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity

Abstract

A parity assist circuit that provides multiple XOR calculations using a scatter-gather list is disclosed. The parity assist circuit includes a control circuit that obtains a plurality of source operands in response to a scatter-gather list, and an XOR engine that provides a plurality of XOR products computed from the supplied source operands. Destination and length parameters in the scatter-gather list are used by the XOR engine to store the XOR computation product and to determine the length of the data in the source and destination blocks to be computed. Preferably, the parity assist circuit is part of a RAID controller that includes a processor and a cache memory. The parity assist circuit preferably utilizes the scatter-gather list to gather required source operands from a memory and to scatter multiple XOR products to the memory before sending an interrupt to the processor or receiving additional setup instructions from the processor, thereby providing rapid and efficient parity calculations and improving overall system performance of the RAID storage subsystem.

Claims

1. A parity assist circuit for use with a controller, comprising:

a scatter-gather list processor adapted for coupling to a cache memory of the controller to process a scatter-gather list each entry of which specifies parameters of at least one XOR computation to be performed; and

an XOR engine coupled to said scatter-gather list processor that produces an XOR product of data stored in the cache memory in accordance with parameters supplied by said scatter-gather list processors,

wherein the parity assist circuit is operable in accordance with parameters supplied by said scatter-gather list processor to read data previously stored in the cache memory by operation of the counter, and

wherein the parity assist circuit is operable to read the data to compute the XOR product without transferring the read data to a device external to the controller, and

wherein the parity assist circuit is configurable to generate a single interrupt applied to a CPU of the controller regardless of the number of XOR products computer by its operation.

2. The circuit of claim 1 further comprising:

registers for defining parameters for an XOR computation; and

a control circuit coupled to said scatter-gather list processor and coupled to said XOR engine and coupled to said registers wherein said scatter-gather list is defined by values in said registers.

3. The circuit of claim 2 wherein said registers include:

a plurality of operand source registers wherein a value in each operand source register of said plurality of operand source registers points to a list of operand source values to be used in XOR computations; and

a destination register wherein a value in said destination register points to a list of destination values corresponding to said list of operand source values and wherein each destination value of said list of destination values points at a location for storage of the XOR product of corresponding operand source values in the lists of operand source values.

4. The circuit of claim 3 wherein said registers further include:

a length register wherein a value in said length register points to a list of length values corresponding to said operand source values and wherein each length value identifies a number of data elements in said operand source values to be used in an XOR computation.

5. The circuit of claim 3 wherein a length value for each said XOR computation is derived from a value associated with a corresponding one of said operand source values.

6. The circuit of claim 3 further comprising:

a local memory within said parity assist circuit and coupled to said control circuit and coupled to said scatter-gather list processor wherein said scatter-gather list is initially stored external to said parity assist circuit and wherein said control circuit reads said scatter-gather list and stores said scatter-gather list in said local memory for processing by said scatter-gather list processor.

7. The circuit of claim 6 wherein said scatter-gather list processor is operable to program said registers with parameters derived from said scatter-gather lists in said local memory to enable said XOR engine to perform requested XOR operations.

8. The circuit of claim 7 wherein said scatter-gather list is iteratively operable to program a plurality of XOR operations in sets of said registers.

9. The circuit of claim 7 wherein said registers comprise:

a first portion exposed for programming by devices external to said circuit; and

a second portion hidden from said devices external to said circuit.

10. The circuit of claim 9 wherein said scatter-gather list processor is operable to program said registers in said second portion with parameters derived from said scatter-gather lists in said local memory to enable said XOR engine to perform requested XOR operations.

11. The circuit of claim 1 further comprising:

a control circuit coupled to said scatter-gather list processor and coupled to said XOR engine wherein the control circuit notifies an attached host of completion of XOR operations only at the completion of all XOR operations specified in said scatter-gather list.

12. The circuit of claim 1 further comprising:

a local memory within said circuit and coupled to said scatter-gather list processor and coupled to said XOR engine wherein said scatter-gather list is initially stored external to said parity assist circuit and wherein said scatter-gather list processor reads said scatter-gather list and stores said scatter-gather list in said local memory for processing by said scatter-gather list processor and by said XOR engine.

13. The circuit of claim 12 wherein said scatter-gather list includes a plurality of elements and wherein each element of said plurality of elements defines all said parameters of an XOR operation.

14. A disk array storage system including:

a controller for controlling said disk array system; and

multiple disk drives coupled to said controller for storing data on behalf of a host computer,

wherein said controller includes;

a processor;

a cache memory for storing data; and

a parity assist circuit,

wherein said parity assist circuit includes;

a scatter-gather list processor to process a scatter-gather list each entry of which specifies parameters of at least one XOR computation to be performed on a portion of the data; and

an XOR engine coupled to said scatter-gather list processor that produces an XOR product in accordance with parameters supplied by said scatter-gather list processor,

wherein the parity assist circuit is operable in accordance with parameters supplied by said scatter-gather list processor to read data previously stored in the cache memory by operation of the controller, and

wherein the parity assist circuit is operable to read the data to compute an XOR product without transferring the read data to a device external to the controller, and

wherein the parity assist circuit is configurable to generate a single interrupt applied to the processor regardless of the number of XOR products computed by its operation.

15. The system of claim 14 wherein the parity assist circuit further comprises:

registers for defining parameters for an XOR computation; and

a control circuit coupled to said scatter-gather list processor and coupled to said XOR engine and coupled to said registers wherein said scatter-gather list is defined by values in said registers.

16. The system of claim 15 wherein said registers include:

a plurality of operand source registers wherein a value in each operand source register of said plurality of operand source registers points to a list of operand source values to be used in XOR computations;

a destination register wherein a value in said destination register points to a list of destination values corresponding to said list of operand source values and wherein each destination value of said list of destination values points at a location for storage of the XOR product of corresponding operand source values in the lists of operand source values; and

a length register wherein a value in said length register points to a list of length values corresponding to said operand source values and wherein each length value identifies a number of data elements in said operand source values to be used in an XOR computation.

17. The system of claim 16 wherein the parity assist circuit further comprises:

a local memory within said circuit and coupled to said control circuit and coupled to said scatter-gather list processor wherein said scatter-gather list is initially stored external to said parity assist circuit and wherein said control circuit reads said scatter-gather list and stores said scatter-gather list in said local memory for processing by said scatter-gather list processor.

18. The system of claim 17 wherein said scatter-gather list processor is operable to program said registers with parameters derived from said scatter-gather lists in said local memory to enable said XOR engine to perform requested XOR operations.

19. The system of claim 18 wherein said scatter-gather list is iteratively operable to program a plurality of XOR operations in sets of said registers.

20. The system of claim 18 wherein said registers comprise:

a first portion exposed for programming by devices external to said circuit; and

a second portion hidden from said devices external to said circuit.

21. The system of claim 20 wherein said scatter-gather list processor is operable to program said registers in said second portion with parameters derived from said scatter-gather lists in said local memory to enable said XOR engine to perform requested XOR operations.

22. The system of claim 14 further comprising:

a control circuit coupled to said scatter-gather list processor and coupled to said XOR engine wherein the control circuit notifies an attached host of completion of XOR operations only at the completion of all XOR operations specified in said scatter-gather list.

23. The system of claim 14 further comprising:

a local memory within said circuit and coupled to said scatter-gather list processor and coupled to said XOR engine wherein said scatter-gather list is initially stored external to said parity assist circuit and wherein said scatter-gather list processor reads said scatter-gather list and stores said scatter-gather list in said local memory for processing by said scatter-gather list processor and by said XOR engine.

24. The system of claim 23 wherein said scatter-gather list includes a plurality of elements and wherein each element of said plurality of elements defines all said parameters of an XOR operation.

25. The system of claim 23 wherein said scatter-gather list is used by said processor for purposes within said system in addition to use by said parity assist circuit.

26. A parity assist circuit for use with a controller comprising:

an XOR engine for computing XOR parity values using data stored in a cache memory of the controller in accordance with parameters applied to the XOR engine;

scatter-gather means for processing a scatter-gather list having at least one entry to provide said parameters to said XOR engine; and

control means for sequencing through all entries of said scatter-gather list to compute XOR parity values for corresponding to all entries in said scatter-gather list,

wherein the parity assist circuit is operable in accordance with parameters supplied by said scatter-gather means to read data previously stored in the cache memory by operation of the controller, and

wherein the parity assist circuit is operable to read the data to computer an XOR parity value without transferring the read data to a device external to the controller, and

wherein the parity assist circuit is configurable to generate a single interrupt applied to a CPU of the controller regardless of the number of XOR parity values computed by operation of the parity assist circuit.

27. The parity assist circuit of claim 26 further comprising:

a local memory within said parity assist circuit; and

means for copying said scatter-gather list from an external memory to said local memory for further processing by said scatter-gather means.

28. The parity assist circuit of claim 27 further comprising:

register means for storing said parameters wherein said scatter-gather means programs said register means with said parameters for each entry in said scatter-gather list as said control means sequences through each of said entries in said scatter-gather list.

29. The parity assist circuit of claim 28 wherein said register means includes:

a plurality of operand register means wherein each of said-plurality of rand register means is programmed by said scatter-gather means to point to a corresponding operand parameter of a desired XOR computation;

a destination register means programmed to point to a destination parameter of a desired XOR computation; and

a length register means programmed to indicate a length parameter of data pointed to by each of said plurality of operand register means and pointed to be said destination register means corresponding to a desired XOR computation.

30. A method operable within a parity assist circuit of a storage controller for computing parity values comprising the steps of:

storing data in a cache memory of the storage controller;

providing a scatter-gather list to said parity assist circuit wherein said scatter-gather list has at least one entry defining a desired XOR computation of a portion of the data;

sequencing through each of said entries in said scatter-gather list to perform a sequence of desired XOR computations defined by the entries of said scatter-gather list wherein the parity assist circuit is operable during sequencing to read the data stored in the cache memory to compute an XOR parity sum without transferring the read data to a device external to the controller; and

generating as few as a single interrupt applied to a processor associated with the controller regardless of the number of XOR computations defined by entries of said scatter-gather list.

31. The method of claim 30, wherein said parity assist circuit includes a local memory and wherein the method further comprises the step of:

copying said scatter-gather list from an external memory to said local memory.

32. The method of claim 30 wherein said parity assist circuit includes registers used to define parameters of an XOR operation by said XOR engine and wherein the method step of sequencing includes the step of:

programming said registers with parameters of an XOR operation in accordance with values supplied in each entry of said scatter-gather list.

33. The method of claim 32 wherein said registers include a plurality of source operand registers and a destination register and a length register and wherein the step of programming includes:

programming each of said plurality of source operand registers with a source operand value from an entry of said scatter-gather list,

programming said destination register with a destination value from said entry of said scatter-gather list; and

programming said length register with a length value from said entry of said scatter-gather list.

34. The method of claim 30 further comprising the step of:

notifying the processor of the completion of requested XOR operation with a single generated interrupt only upon completion of the step of sequencing through each of said entries in said scatter-gather list.