Adaptive keeper sizing for dynamic circuits based on fused process corner data
First Claim
1. A semiconductor die having adaptive keeper logic, comprising:
- a plurality of dynamic circuits, each dynamic circuit including an adaptive keeper circuit capable of being adjusted based on a bit code;
a process corner databank having process corner data that indicates a process corner of the semiconductor die; and
a test processor unit in communication with the process corner databank and the plurality of dynamic circuits, the test processor unit being capable of obtaining process corner data from the process corner databank, the test processor unit further being capable of providing a bit code based on the process corner data to the plurality of dynamic circuits.
2 Assignments
0 Petitions
Accused Products
Abstract
An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.
26 Citations
12 Claims
-
1. A semiconductor die having adaptive keeper logic, comprising:
-
a plurality of dynamic circuits, each dynamic circuit including an adaptive keeper circuit capable of being adjusted based on a bit code;
a process corner databank having process corner data that indicates a process corner of the semiconductor die; and
a test processor unit in communication with the process corner databank and the plurality of dynamic circuits, the test processor unit being capable of obtaining process corner data from the process corner databank, the test processor unit further being capable of providing a bit code based on the process corner data to the plurality of dynamic circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method for optimizing a keeper circuit for use in a dynamic circuit, comprising the operations of:
-
obtaining process corner data for a die from a databank present on the die;
translating the process corner data into a bit code, the bit code indicating a process corner of the die; and
adding particular secondary keeper transistors to a first keeper transistor, the particular secondary keeper transistors being selected using the bit code. - View Dependent Claims (10, 11, 12)
-
Specification