Sub-micron high input voltage tolerant input output (I/O) circuit

• US 6,914,456 B2
• Filed: 12/19/2002
• Issued: 07/05/2005
• Est. Priority Date: 01/09/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ajit, Janardhanan S.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US10/325,519
• Publication Number:
  US 20030094980A1
• Time in Patent Office: 929 Days
• Field of Search: 327/108, 327/110, 327/112, 327/534, 327/537, 326/21, 326/27, 326/82, 326/26, 326/83, 326/86, 326/81
• US Class Current: 327/108
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Claims

1. An apparatus for biasing a device well the apparatus comprising:

a V_PAD input that accepts an input/output pad voltage VPAD;

a bias circuit that generates a bias voltage at a bias circuit output; and

a well biasing circuit that couples the device well to be biased to a power supply voltage V_DDO if the bias voltage is less than the power supply voltage and the Vpad when Vpad is greater than a comparison voltage.

2. The apparatus of claim 1 wherein the comparison voltage is equal to a power supply voltage (V_DDO) minus a threshold.

3. The apparatus of claim 1 wherein the bias circuit comprises:

a first bias circuit device that couples the bias circuit output to Bias_—

1 when Bias_—

1 is less than the power supply voltage; and

a second bias circuit device that couples the bias circuit output to the pad voltage Vpad when Vpad is greater than the comparison voltage.

4. The apparatus of claim 2 further comprising a PMOS device and an NMOS device serially coupled between the power supply voltage and an intermediate voltage, wherein an output node coupled between the PMOS device and the NMOS device outputs the comparison voltage.

5. The apparatus of claim 4 wherein the threshold voltage equals voltage drop across the PMOS device.

6. The apparatus of claim 1 wherein the well biasing circuit comprises a first PMOS device and wherein the first PMOS device couples the well to be biased to the power supply voltage (V_DDO) the bias voltage is less than the power supply voltage.

7. The apparatus of claim 6 wherein the well biasing circuit further comprises a second PMOS device and wherein the second PMOS device couples the well to be biased to the pad voltage Vpad when Vpad is greater than the comparison voltage.

8. An apparatus for providing a well biasing voltage, the apparatus comprising:

a supply voltage V_DDO input for accepting a supply voltage;

a V_PAD input for accepting the voltage on an I/O pad;

a bias output for providing the well biasing voltage wherein the well biasing voltage is equal to V_DDO when V_PAD is less than V_DDO minus a threshold voltage and V_PAD otherwise; and

a PMOS device and an NMOS device serially coupled between the supply VD_DO and an intermediate voltage, wherein an output node coupled between the PMOS device d the NNOS device outputs the supply voltage minus the threshold voltage.

9. The apparatus of claim 8 wherein the threshold voltage equals voltage drop across the PMOS device.