Sub-micron high input voltage tolerant input output (I/O) circuit
First Claim
1. An apparatus for biasing a device well the apparatus comprising:
- a VPAD input that accepts an input/output pad voltage VPAD;
a bias circuit that generates a bias voltage at a bias circuit output; and
a well biasing circuit that couples the device well to be biased to a power supply voltage VDDO if the bias voltage is less than the power supply voltage and the Vpad when Vpad is greater than a comparison voltage.
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Abstract
A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.
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Citations
9 Claims
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1. An apparatus for biasing a device well the apparatus comprising:
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a VPAD input that accepts an input/output pad voltage VPAD;
a bias circuit that generates a bias voltage at a bias circuit output; and
a well biasing circuit that couples the device well to be biased to a power supply voltage VDDO if the bias voltage is less than the power supply voltage and the Vpad when Vpad is greater than a comparison voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus for providing a well biasing voltage, the apparatus comprising:
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a supply voltage VDDO input for accepting a supply voltage;
a VPAD input for accepting the voltage on an I/O pad;
a bias output for providing the well biasing voltage wherein the well biasing voltage is equal to VDDO when VPAD is less than VDDO minus a threshold voltage and VPAD otherwise; and
a PMOS device and an NMOS device serially coupled between the supply VDDO and an intermediate voltage, wherein an output node coupled between the PMOS device d the NNOS device outputs the supply voltage minus the threshold voltage. - View Dependent Claims (9)
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Specification