Triple resistor string DAC architecture

• US 6,914,547 B1
• Filed: 05/04/2004
• Issued: 07/05/2005
• Est. Priority Date: 05/04/2004
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Swaroop, Prem S, Jha, Kaushal Kumar, Raychaudhuri, Arindam
• Primary Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US10/838,806
• Time in Patent Office: 427 Days
• Field of Search: 341/144, 341/154, 341/145, 341/159
• US Class Current: 341/144
• CPC Class Codes: H03M 1/682 both converters being of the unary decoded type
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals

Abstract

A technique to provide a higher resolution DAC architecture for converting an N-bit digital word to a corresponding analog voltage signal without increasing chip area and switching capacitance. In one example embodiment, this is accomplished by using a triple string converter. In the triple string converter, a triple switching tree is coupled to a triple resistor string and to an analog output. Each switching tree includes a plurality of switches and each resistor string includes a plurality of corresponding resistors. A logic decoder coupled to the triple switching tree receives an N-bit digital word and generates a digital signal. The plurality of switches in each switching tree is substantially simultaneously controlled by the digital signal to output a range of corresponding analog voltage signals when the triple resistor string is connected across a voltage supply.

Claims

1. A digital-to-analog converter, comprising:

a triple switching tree switchably coupled to a triple resistor string and to an analog output,

wherein the triple resistor string includes a first resistor string having a first plurality of resistors for coupling across the voltage supply, a second resistor string having a second plurality of resistors, and a third resistor string having a third plurality of resistors, and

wherein the triple switching tree comprises a first switching network comprising a first mirror-imaged plurality of switches, wherein each of the first mirror-imaged plurality of switches having an input connected to one of the first plurality of resistors and an output to couple across the second resistor string;

a second switching network comprising a second mirror-imaged plurality of switches, wherein each of the second mirror-imaged plurality of switches having an input connected to one of the second plurality of resistors and an output to couple across the third resistor string; and

a third switching network comprising a third mirror-imaged plurality of switches, wherein each of the mirror-imaged plurality of switches having an input connect to one of the third plurality of resistors and an output to connect to the analog output,

wherein the plurality of switches in each branch is substantially simultaneously controlled by an N-bit digital word to output a range of corresponding analog voltage signals, and wherein the triple switching tree is operable when the triple resistor string is coupled across a voltage supply.

2. The digital-to-analog converter of claim 1, wherein the first switching network is controlled by most significant bits (MSBs) and the second and third switching networks are controlled by higher order and lower order least significant bits (LSBs) in the N-bit digital word, respectively.

3. The digital-to-analog converter of claim 1, wherein the switches in the first, second, and third plurality of switching networks are selected from the group consisting of CMOS transmission gates, NMOS transistors, and PMOS transistors.

4. A digital-to-analog converter circuit, comprising:

a first resistor string having a first plurality of resistors to couple across a voltage supply;

a second resistor string having a second plurality of resistors;

a third resistor string having a third plurality of resistors;

a first switching network comprising a first mirror-imaged plurality of switches, wherein each of the first mirror-imaged plurality of switches having an input connected to one of the first plurality of resistors and an output to couple across the second resistor string;

a second switching network comprising a second mirror-imaged plurality of switches, wherein each of the second mirror-imaged plurality of switches having an input connected to one of the second plurality of resistors and an output to couple across the third resistor string; and

a third switching network comprising a third mirror-imaged plurality of switches, wherein each of the mirror-imaged plurality of switches having an input connect to one of the third plurality of resistors and an output to connect to a common output.

5. The circuit of claim 4, further comprising:

a logic decoder to couple to the first, second, and third switching networks, wherein the logic decoder to receive a digital input and to output first, second, and third sets of logic signals, and wherein the first, second, and third switching networks to receive the first, second, and third sets of logic signals and select one of the first, second, and third plurality of resistors via the first, second, and third mirror-imaged plurality of switches coupled to the associated first, second, and third plurality of resistors, respectively.

6. The circuit of claim 5, wherein the digital input comprises an N-bit digital word, wherein the N-bit digital word comprises MSBs, higher order LSBs, and lower order LSBs, wherein the logic decoder produces the first, second, and third sets of logic signals as a function of the received MSBs, higher order LSBs, and lower order LSBs.

7. The circuit of claim 4, wherein the switches in the first, second, and third plurality of switching networks are selected from the group consisting of CMOS transmission gates, NMOS transistors, and PMOS transistors.

8. The circuit of claim 7, wherein the switches in the first, second, and third plurality of switching networks are of varying sizes.

9. The circuit of claim 7, wherein the switches in the first, second, and third plurality of switching networks have an on-resistance of about a fraction of a unit resistance value of the first, second, and third resistor strings.

10. A digital-to-analog converter for converting a digital word into a corresponding analog signal, comprising:

a first resistor string having a first plurality of resistors to couple across a voltage supply;

a second resistor string having a pair of terminals, wherein the second resistor string includes a second plurality of resistors;

a third resistor string having a pair of terminals, wherein the third resistor string includes a third plurality of resistors;

a first switching network comprising a first mirror-imaged plurality of switches to couple to a voltage produced across a selected one of the first plurality of resistors via the first mirror-imaged plurality of switches coupled to the associated first plurality of resistors, wherein the first switching network is coupled to the pair of terminals in the second resistor string, wherein the second plurality of resistors produces voltages in response to a current passing via the first resistor string to the second resistor string via the first switching network;

a second switching network comprising a second mirror-imaged plurality of switches to couple to a voltage produced across a selected one of the second plurality of resistors via the second mirror-imaged plurality of switches coupled to the associated second plurality of resistors, wherein the second switching network is coupled to the pair of terminals in the third resistor string, wherein the third plurality of resistors produces voltages in response to a current passing via the second resistor string to the third resistor string via the second switching network; and

a third switching network comprising a third mirror-imaged plurality of switches, wherein each of the third mirror-imaged plurality of switches having an input connected to one of the third plurality of resistors and an output to connect to a common output, wherein the third switching network to couple to one of the voltages produced by a selected one of the third plurality of resistors to the common output.

11. The digital-to-analog converter of claim 10, wherein the switches in the first, second, third plurality of switching networks are selected from the group consisting of CMOS transmission gates, NMOS transistors, and PMOS transistors.

12. The digital-to-analog converter of claim 10, wherein the first plurality of resistors comprises:

2^M resistors in the first resistor string, wherein M being a number of MSBs in an N-bit digital word.

13. The digital-to-analog converter of claim 12, wherein the second plurality of resistors comprises:

2^P resistors in the second resistor string, wherein P being a number of higher order LSBs in an N-bit digital word.

14. The digital-to-analog converter of claim 13, wherein the third plurality of resistors comprises:

2^K−

1 resistors in the third resistor string, wherein K being a number of lower order LSBs in an N-bit digital word.

15. The digital-to-analog converter of claim 14, wherein the N-bit digital word comprises:

N-bit digital word=M MSBs +P higher order LSBs+K lower order LSBs.

16. A digital-to-analog converter with cascaded coarse and fine resistor divider strings, comprising:

a primary resistor string having a first plurality of resistors to couple across a voltage supply;

a secondary resistor string having a pair of terminals, wherein the secondary resistor string includes a second plurality of resistors;

a tertiary resistor string having a pair of terminals, wherein the tertiary resistor string includes a third plurality of resistors;

a primary switching network comprising a plurality of switches to couple to a voltage produced across a selected one of the first plurality of resistors in response to a first set of logic signals via the first plurality of switches coupled to the associated first plurality of resistors, wherein the primary switching network is coupled to the pair of terminals in the secondary resistor string, wherein the second plurality of resistors produces voltages in response to a current passing via the primary resistor string to the secondary resistor string via the primary switching network;

a secondary switching network comprising a plurality of switches to couple to a voltage produced across a selected one of the second plurality of resistors in response to a second set of logic signals via the second plurality of switches coupled to the associated second plurality of resistors, wherein the secondary switching network is coupled to the pair of terminals in the tertiary resistor string, wherein the third plurality of resistors produces voltages in response to a current passing via the secondary resistor string to the tertiary resistor string via the secondary switching network; and

a tertiary switching network comprising a plurality of switches, wherein each of the third plurality of switches having an input connected to one of the third plurality of resistors and an output to connect to a common output, wherein the tertiary switching network to couple to one of the voltages produced by a selected one of the tertiary plurality of resistors to the common output in response to a third set of logic signals.

17. The digital-to-analog converter of claim 16 further comprising:

a logic decoder to couple to the primary, secondary, and tertiary switching networks, wherein the logic decoder receives a digital input and outputs the first, second and third sets of logic signals.

18. The digital-to-analog converter of claim 17, wherein the digital input comprises an N-bit digital word, wherein the N-bit digital word comprises an M number of MSBs, a P number of higher order LSBs, and a K number of lower order LSBs, wherein the logic decoder produces the first, second, and third sets of logic signals as a function of the received M number of MSBs, P number of higher order LSBs, and K number of lower order LSBs.

19. An integrated circuit, comprising:

a first resistor string having a first plurality of resistors to couple across a voltage supply;

a second resistor string having a second plurality of resistors;

a third resistor string having a third plurality of resistors;

a first switching network comprising a first mirror-imaged plurality of switches, wherein each of the first mirror-imaged plurality of switches having an input connected to one of the first plurality of resistors and an output to couple across the second resistor string;

a second switching network comprising a second mirror-imaged plurality of switches, wherein each of the second mirror-imaged plurality of switches having an input connected to one of the second plurality of resistors and an output to couple across the third resistor string;

a third switching network comprising a third mirror-imaged plurality of switches, wherein each of the mirror-imaged plurality of switches having an input connect to one of the third plurality of resistors and an output to connect to a common output; and

a logic decoder to couple to the first, second, and third switching networks, wherein the logic decoder receives a digital input and outputs first, second, and third sets of logic signals as a function of the digital input, and wherein the first, second, and third switching networks receive the first, second, and third sets of logic signals and selects one of the first, second, and third plurality of resistors via the first, second, and third mirror-imaged plurality of switches coupled to the associated first, second, and third plurality of resistors, respectively.

20. The circuit of claim 19, wherein the switches in the first, second, and third plurality of switching networks are selected from the group consisting of CMOS transmission gates, NMOS transistors, and PMOS transistors.

21. The circuit of claim 19, wherein the switches in the first, second, and third plurality of switching networks are of varying sizes.

22. The circuit of claim 19, wherein the switches in the first, second, and third plurality of switching networks have an on-resistance of about a fraction of a nominal resistance value of the first, second, and third resistor strings.