Method and apparatus for digital column fixed pattern noise canceling for a CMOS image sensor

• US 6,914,627 B1
• Filed: 05/27/1998
• Issued: 07/05/2005
• Est. Priority Date: 05/27/1998
• Status: Expired due to Term

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Dong, Kimble
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Tillery, Rashawn N.
• Application Number:
  US09/085,519
• Time in Patent Office: 2,596 Days
• Field of Search: 348/248, 348/249, 348/241, 348/243, 348/246, 348/247, 348/607, 348301-310, 378/98.8
• US Class Current: 348/248
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise

Abstract

The present invention is directed to a method and apparatus for reading out signals from a MOS image sensor. The invention allows for a relatively high fixed pattern noise canceling rate, even in low light environments. The invention includes a digital processing structure for processing the signals from a pixel array. The pixel array includes a reference row that is formed by being covered by a light shield or black layer to cover the pixels of the reference row from light. The signals from the reference row are converted to digital values and stored in fixed pattern noise storage circuitry. Then, as each of the remaining rows of the pixel array are read out, they are converted to digital values and the digital reference row signals are subtracted therefrom to produce data image signals that are relatively free of fixed pattern noise. Thus, the fixed pattern noise canceling rate is made to depend on the precision of an analog-to-digital converter, rather than the process variations of an analog subtraction circuit.

Claims

1. A MOS image sensor comprising:

a pixel array formed from a plurality of individual pixels organized as rows and columns, said pixel array including a reference row;

analog signal processing circuitry for reading out analog signals from the pixel array;

an analog-to-digital converter for converting analog signals from the analog signal processing circuitry into digital signals;

fixed pattern noise storage circuitry for storing digital signals representative of the signals from the reference row of the pixel array; and

a fixed pattern noise canceling processor for subtracting the digital reference row signals stored in the fixed pattern noise storage circuitry from the digital signals representative of the signals from the other pixels in the pixel array.

2. The image sensor of claim 1, wherein the reference row of the pixel array is formed by being covered with a light shield.

3. The image sensor of claim 1, wherein the reference row of the image sensor is located near an edge of the pixel array.

4. The image sensor of claim 1, wherein the circuitry of the MOS image sensor is fabricated on a single MOS chip.

5. The image sensor of claim 1, wherein the analog-to-digital converter has at least 10-bit capability.

6. The image sensor of claim 1, wherein the fixed pattern noise storage circuitry receives a write control signal, the write control signal causing the fixed pattern noise storage circuitry to write the digital signals representative of the signals received from the reference row into the fixed pattern noise storage circuitry.

7. The image sensor of claim 6, wherein the fixed pattern noise storage circuitry also receives a read control signal, the read control signal causing the fixed pattern noise storage circuitry to read out the digital signals representative of the signals from the reference row of the pixel array.

8. The image sensor of claim 7, wherein the write control signal and the read control signal have similar timing such that the exposure time of the reference row is approximately the same as the exposure time of the remaining rows of the pixel array.

9. The image sensor of claim 7, wherein the fixed pattern noise canceling processor receives a field control signal, the field control signal coordinating the timing between the reading of different fields.

10. A digital processing structure for processing signals from a pixel array, said pixel array including a plurality of individual pixels organized as rows and columns, said pixels outputting pixel signals, said pixel array having a reference row, said digital processing structure comprising:

an analog-to-digital converter for converting the analog signals from the pixel array into digital signals;

fixed pattern noise storage circuitry for storing digital signals received from the analog-to-digital converter representative of the signals from the reference row of the pixel array; and

a fixed pattern noise canceling processor for subtracting the signals stored in the fixed pattern noise storage circuitry from the digital signals representative of the analog signals from the remaining rows of the pixel array.

11. The digital processing structure of claim 10, wherein the analog-to-digital converter has at least 10-bit capability.

12. The digital processing structure of claim 10, wherein the fixed pattern noise storage circuitry receives a write control signal, the write control signal causing the fixed pattern noise storage circuitry to write the digital signals representative of the signals received from the reference row into the fixed pattern noise storage circuitry.

13. The digital processing structure of claim 12, wherein the fixed pattern noise storage circuitry also receives a read control signal, the read control signal causing the fixed pattern noise storage circuitry to read out the digital signals representative of the signals from the reference row of the pixel array.

14. The digital processing structure of claim 13, wherein the write control signal and the read control signal have similar timing such that the exposure time of the reference row is approximately the same as the exposure time of the remaining rows of the pixel array.

15. The digital processing structure of claim 13, wherein the fixed pattern noise canceling processor receives a field control signal, the field control signal coordinating the timing between the reading of different fields.

16. The digital processing structure of claim 10, wherein the digital processing structure and the pixel array are formed on a single MOS imaging chip.

17. A method for reading out signals from an image sensor having a pixel array of a plurality of individual pixels organized as a plurality of rows and columns, said pixel array having a reference row, said method comprising the steps of:

(a) reading out the signals from the reference row of the pixel array;

(b) converting the reference row signals to digital values and storing the digital reference row signals;

(c) reading the signals from an additional row of the pixel array;

(d) converting the additional row signals to digital values; and

(e) subtracting the stored digital reference row signals from the digital additional row signals.

18. The method of claim 17, wherein steps (c)-(e) are repeated for additional rows from the pixel array until all of the rows of the pixel array have been read out.

19. The method of claim 18, wherein after all of the rows of the pixel array have been read out, the entire process starting with steps (a) and (b) is repeated.

20. The method of claim 17, wherein the timing for the reading of the reference row in step (a) is similar to the timing for the reading of an additional row in step (c), such that the exposure time of the reference row is the same as for an additional row.

21. The method of claim 17, wherein the digital conversion is done with at least 10-bit capability.

22. A method for compensating for fixed pattern noise in a MOS image sensor, said MOS image sensor having a pixel array of a plurality of individual pixels organized as a plurality of rows and columns, said pixel array having a reference row, said method comprising the steps of:

(a) reading out the signals from the reference row of a pixel array;

(b) converting the reference row signals to digital values and storing the digital reference row signals; and

(c) using the stored digital reference row signals to compensate for fixed pattern noise in the signals from additional rows of the pixel array.

23. The method of claim 22, wherein the method of compensating for fixed pattern noise in step (c) comprises converting the additional row signals to digital values and subtracting the stored digital reference row signals from the digital additional row signals.

24. The method of claim 22, wherein the digital conversion is done with at least 10-bit capability.