Distributed write data drivers for burst access memories

• US 6,914,830 B2
• Filed: 08/29/2002
• Issued: 07/05/2005
• Est. Priority Date: 12/23/1994
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Merritt, Todd A.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/231,682
• Publication Number:
  US 20020196668A1
• Time in Patent Office: 1,041 Days
• Field of Search: 365/189.01, 365/189.05, 365/193, 365/230.01, 365/233, 365/202, 365/204
• US Class Current: 365/189.05
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near a nay sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

Claims

1. A method of writing data into a memory device comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines

of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close

proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in

response to deasserting the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the

gating; and

storing data in a memory cell in response to driving data.

2. The method of claim 1, wherein the recited steps are initiated in the recited order.

3. The method of claim 1, wherein the memory device is a burst extended data out dynamic random access memory device.

4. The method of claim 1, wherein gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal comprises:

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the

equilibrate signal.

5. The method of claim 4, wherein logically combining the version of the latched write enable signal and the version of the equilibrate signal comprises nanding the version of the latched write enable signal and the version of the equilibrate signal.

6. The method of claim 1, wherein the memory device includes a sense amplifier and gating occurs in logic circuitry proximate to the sense amplifier.

7. A method of writing data into a memory device comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal, wherein gating the write enable signal comprises;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating; and

storing data in a memory cell in response to driving data.

8. The method of claim 7, wherein the recited steps are initiated in the recited order.

9. The method of claim 7, further comprising gating the equilibration signal with a read command signal and a write control signal to ensure that the equilibration signal does not transition prior to the write control signal becoming invalid.

10. The method of claim 7, wherein the memory device is a burst extended data out dynamic random access memory device.

11. A method of writing data into a memory device comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal, wherein gating the write enable signal comprises;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal, wherein logically combining the version of the latched write enable signal and the version of the equilibrate signal comprises nanding the version of the latched write enable signal and the version of the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating; and

storing data in a memory cell in response to driving data.

12. The method of claim 11, wherein the recited steps are initiated in the recited order.

13. The method of claim 11, further comprising gating the equilibration signal with a read command signal and a write control signal to ensure that the equilibration signal does not transition prior to the write control signal becoming invalid.

14. A method of writing data into a memory device, comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating; and

storing data in a memory cell in response to driving data,

wherein writing occurs as part of a burst write access and the write enable signal remains active throughout the burst write access.

15. The method of claim 14, wherein the recited steps are initiated in the recited order.

16. The method of claim 14, further comprising gating the equilibration signal with a read command signal and a write control signal to ensure that the equilibration signal does not transition prior to the write control signal becoming invalid.

17. The method of claim 14, wherein the memory device is a burst extended data out dynamic random access memory device.

18. A method of writing data into a memory device, comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal, wherein gating the write enable signal comprises;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating; and

storing data in a memory cell in response to driving data.

19. The method of claim 18, further comprising deactivating the write enable signal in response to an /RAS signal being active.

20. The method of claim 18, further comprising gating the equilibration signal with a read command signal and a write control signal to ensure that the equilibration signal does not transition prior to the write control signal becoming invalid.

21. The method of claim 18, wherein the recited steps are initiated in the recited order.

22. A method of writing data into a memory device, comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal, wherein gating the write enable signal comprises;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating;

storing data in a memory cell in response to driving data; and

,

deactivating the write enable signal in response to an /RAS signal and /CAS signal both being active.

23. The method of claim 22, wherein the recited steps are initiated in the recited order.

24. The method of claim 22, further comprising gating the equilibration signal with a read command signal and a write control signal to ensure that the equilibration signal does not transition prior to the write control signal becoming invalid.

25. A method of writing data into a memory device, comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal, wherein gating the write enable signal comprises;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating;

storing data in a memory cell in response to driving data; and

deactivating the write enable signal in response to expiration of a time-out period following a transition of a /CAS signal.

26. The method of claim 25, wherein the recited steps are initiated in the recited order.

27. The method of claim 25, further comprising gating the equilibration signal with a read command signal and a write control signal to ensure that the equilibration signal does not transition prior to the write control signal becoming invalid.

28. A method of writing data into a memory device, comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal, wherein gating the write enable signal comprises;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating;

storing data in a memory cell in response to driving data; and

deactivating the write enable signal at the beginning of each access cycle.

29. The method of claim 28, further comprising gating the equilibration signal with a read command signal and a write control signal to ensure that the equilibration signal does not transition prior to the write control signal becoming invalid.

30. The method of claim 28, wherein the recited steps are initiated in the recited order.

31. A method of writing data into a memory device comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal, wherein gating the write enable signal comprises;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating; and

storing data in a memory cell in response to driving data.

deactivating the write enable signal at the beginning of each access cycle and maintaining the write enable signal inactive within a burst write access for a period of time which is less than an equilibration time.

32. The method of claim 31, wherein the recited steps are initiated in the recited order.

33. A method of writing data into a memory device comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

coupling the equilibrate signal to a plurality of data driver enable circuits located in close proximity and coupled to write data drivers;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal, wherein gating the write enable signal comprises;

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating; and

storing data in a memory cell in response to driving data.

gating the equilibration signal with a read command signal and a write control signal to ensure that the equilibration signal does not transition prior to the write control signal becoming invalid.

34. The method of claim 33, wherein the recited steps are initiated in the recited order.