Flash EEprom system

• US 6,914,846 B2
• Filed: 12/26/2002
• Issued: 07/05/2005
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): HUA, LY
• Application Number:
  US10/331,081
• Publication Number:
  US 20030128618A1
• Time in Patent Office: 922 Days
• Field of Search: 714/8, 714/710, 365/185.12, 365/185.11, 365/227, 365/185.03, 365/230.03, 365/185.19, 365/218, 365/185.09, 365/200, 365/185.33
• US Class Current: 365/230.03
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A method of operating a non-volatile memory system, comprising:

utilizing more than one integrated circuit chip that individually includes a plurality of non-overlapping units of memory cells that are erasable together, the individual units of memory cells storing multiple bytes of data,

selecting a plurality of units of memory cells distributed over more than one of the integrated circuit chips for erase, and

thereafter erasing the selected plurality of units of memory cells together without erasing others of the units of memory cells on said more than one of the integrated circuit chips.

2. The method of claim 1, which additionally comprises thereafter programming multiple bytes of data into individual ones of the selected plurality of units of memory cells.

3. The method of claim 2, wherein programming includes programming individual memory cells into more than two states, wherein the individual memory cells store more than one bit of data.

4. The method of claim 1, wherein erasing the selected units of memory cells includes simultaneously erasing said selected plurality of units of memory cells.

5. The method of claim 1, wherein erasing the selected units of memory cells includes monitoring the states of said selected units of memory cells and individually terminating erasure of the selected units upon detecting that their memory cells have reached an erased state.

6. The method of claim 1, wherein the memory system exists in a card having connecting pins that are removably connectable with a host system.

7. A method of operating a non-volatile memory system, comprising:

utilizing a plurality of integrated circuit chips that each includes a plurality of non-overlapping units of memory cells that are erasable together and that each individually stores multiple bytes of data,

setting a tag for each of multiple units of memory cells distributed over more than one of the plurality of integrated circuit chips for erase, and

thereafter erasing the tagged multiple units of memory cells together without erasing others of the units of memory cells on said more than one of the integrated circuit chips.

8. The method of claim 7, wherein setting a tag for each of the multiple units of memory cells includes setting states of registers that are individually connected to individual ones of the multiple units of memory cells.

9. The method of claim 7, wherein erasing the tagged multiple units of memory cells includes simultaneously erasing the tagged multiple units of memory cells.

10. The method of claim 7, which additionally comprises thereafter programming multiple bytes of data into individual ones of the erased multiple units of memory cells.

11. A non-volatile memory system, comprising:

a plurality of integrated circuit chips that individually includes an array of re-programmable non-volatile memory cells organized into non-overlapping units of a plurality of memory cells wherein the plurality of memory cells of individual units are erasable together, the units of memory cells individually having a capacity to store multiple bytes of data,

a controller on another integrated circuit chip,

a bus connecting said another integrated circuit chip and said plurality of integrated circuit chips, and

logic circuits provided on the plurality of integrated circuit chips and connected with the controller over the bus to cause a plurality of selected units of memory cells on more than one of the plurality of integrated circuit chips to be erased together without erasing others of the units of memory cells on said more than one of the plurality of integrated circuit chips.

12. The memory system of claim 11, wherein the memory cells individually include at least one charge storage element that is programmable into more than two states, whereby more than one bit of data may be stored on individual ones of the charge storage elements.