PLL circuit and optical communication reception apparatus

• US 6,915,081 B2
• Filed: 10/17/2001
• Issued: 07/05/2005
• Est. Priority Date: 10/19/2000
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nishimura, Takashi, Takeshita, Toru
• Primary Examiner(s): Pascal, Leslie
• Assistant Examiner(s): TRAN, DZUNG D
• Application Number:
  US09/978,058
• Publication Number:
  US 20020057479A1
• Time in Patent Office: 1,357 Days
• Field of Search: 398/150, 398/154, 398/155, 398/187, 398/188, 398/197, 398/201, 375/375, 375/376, 375/294, 327/147, 327/156, 329/325
• US Class Current: 398/188
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/191 using at least two different signals from the frequency divider or the counter for determining the time difference H03L7/193, H03L7/195 take precedence

Abstract

The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, stabilized PLL operation is achieved. The PLL circuit includes a phase detection circuit and a frequency detection circuit. The frequency detection circuit includes a pair of D-type flip-flops for sampling first and second clock signals having different phases from each other in synchronism with an input signal at each rising or falling changing point of the input signal for each period, and a control logic circuit for logically operating the signals sampled by the D-type flip-flops and the signals sampled successively subsequently by the D-type flip-flops. The control logic circuit generates an UP pulse signal or a DOWN pulse signal based on a result of the arithmetic operation.

Claims

1. A PLL circuit, comprising:

an oscillator for generating an oscillation frequency signal having a variable oscillation frequency;

a phase detection circuit for comparing the phases of the oscillation frequency signal of said oscillator and an input signal with each other and outputting, based on a result of the comparison, a first phase control signal for advancing the phase of the oscillation frequency signal of said oscillator or a second phase control signal for delaying the phase of the oscillation frequency signal of said oscillator;

a signal generation circuit for generating first and second signals having different phases from each other based on the oscillation frequency signal of said oscillator; and

a frequency detection circuit for fetching the first and second signals generated by said signal generation circuit in synchronism with the input signal for each period of the input signal, logically operating the fetched signals and signals having been fetched in the immediately preceding period and outputting, based on a result of the arithmetic operation, a first frequency control signal for raising the frequency of the oscillation frequency signal of said oscillator or a second frequency control signal for lowering the frequency of the oscillation frequency signal of said oscillator.

2. A PLL circuit according to claim 1, wherein the first and second signals are clock signals.

3. A PLL circuit according to claim 2, wherein the phases of the first and second signals differ from each other by 90 degrees.

4. A PLL circuit according to claim 1, wherein said frequency detection circuit includes a first sampling circuit for fetching the first signal in synchronism with the input signal for each period of the input signal, a second sampling circuit for fetching the second signal in synchronism with the input signal for each period of the input signal, and a control logic circuit for storing the signals fetched by said first and second sampling circuits, logically operating the stored signals and the signals fetched subsequently by said first and second sampling circuits and generating, based on a result of the logical operation, the first frequency control signal or the second frequency control signal.

5. A PLL circuit according to claim 4, wherein said control logic circuit includes a first logical operation circuit for logically operating output signals of said first and second sampling circuits, a first storage circuit for storing an output signal of said first logical operation circuit, a second logical operation circuit for logically operating the output signals of said first and second sampling circuits and the stored signal of said first storage circuit, a third logical operation circuit for logically operating a signal obtained by logical processing of the output signals of said first and second sampling circuit and the stored signal of said first storage circuit, second storage means for storing an output signal of said second logical operation circuit, and third storage means for storing an output signal of said third logical operation circuit.

6. A PLL circuit according to claim 5, wherein each of said first, second and third logical operation circuits includes an OR circuit.

7. A PLL circuit according to claim 5, wherein each of said first, second and third storage circuits includes a flip-flop circuit.

8. A PLL circuit according to claim 7, wherein said flip-flop circuit is a D-type flip-flop.

9. A PLL circuit according to claim 4, wherein said first and second sampling circuits sample the first and second signals, respectively, at a timing of a rising edge or a falling edge of the input signal.

10. A PLL circuit according to claim 4, wherein each of said first and second sampling circuits includes a flip-flop circuit.

11. A PLL circuit according to claim 10, wherein said flip-flop is a D-type flip-flop.

12. A PLL circuit according to claim 11, wherein the D-type flip-flops fetch the first and second signals at a timing of a rising edge of a clock input thereto.

13. An optical communication reception apparatus, comprising:

light reception means for receiving an optical signal, converting the optical signal into an electric signal and outputting the electric signal;

a PLL circuit for producing a clock signal synchronized with the output signal of said light reception means; and

a retiming circuit for retiming the output signal of said light reception means based on the clock signal produced by said PLL circuit;

said PLL circuit including an oscillator for generating an oscillation frequency signal having a variable oscillation frequency, a phase detection circuit for comparing the phases of the oscillation frequency signal of said oscillator and an input signal with each other and outputting, based on a result of the comparison, a first phase control signal for advancing the phase of the oscillation frequency signal of said oscillator or a second phase control signal for delaying the phase of the oscillation frequency signal of said oscillator, a signal generation circuit for generating first and second signals having different phases from each other based on the oscillation frequency signal of said oscillator, and a frequency detection circuit for fetching the first and second signals generated by said signal generation circuit in synchronism with the input signal for each period of the input signal, logically operating the fetched signals and signals having been fetched in the immediately preceding period and outputting, based on a result of the arithmetic operation, a first frequency control signal for raising the frequency of the oscillation frequency signal of said oscillator or a second frequency control signal for lowering the frequency of the oscillation frequency signal of said oscillator.

14. An optical communication reception apparatus according to claim 13, wherein the first and second signals are clock signals.

15. An optical communication reception apparatus according to claim 14, wherein the phases of the first and second signals differ from each other by 90 degrees.

16. An optical communication reception apparatus according to claim 13, wherein said frequency detection circuit includes a first sampling circuit for fetching the first signal in synchronism with the input signal for each period of the input signal, a second sampling circuit for fetching the second signal in synchronism with the input signal for each period of the input signal, and a control logic circuit for storing the signals fetched by said first and second sampling circuits, logically operating the stored signals and the signals fetched subsequently by said first and second sampling circuits and generating, based on a result of the logical operation, the first frequency control signal or the second frequency control signal.

17. An optical communication reception apparatus according to claim 16, wherein said control logic circuit includes a first logical operation circuit for logically operating output signals of said first and second sampling circuits, a first storage circuit for storing an output signal of said first logical operation circuit, a second logical operation circuit for logically operating the output signals of said first and second sampling circuits and the stored signal of said first storage circuit, a third logical operation circuit for logically operating a signal obtained by logical processing of the output signals of said first and second sampling circuit and the stored signal of said first storage circuit, second storage means for storing an output signal of said second logical operation circuit, and third storage means for storing an output signal of said third logical operation circuit.

18. An optical communication reception apparatus according to claim 16, wherein said first and second sampling circuits sample the first and second signals, respectively, at a timing of a rising edge or a falling edge of the input signal.