Shared peripheral architecture
First Claim
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1. An embedded computing system, comprising:
- a plurality of processors;
a bus coupling to a plurality of peripheral units;
a multiplexor for coupling each of the plurality of processors to the bus in response to an owner signal; and
a set of peripheral-share registers wherein each member of the set resides at and is associated with a particular one of the plurality of peripheral units and includes an entry holding a state value indicating which of the plurality of processors currently owns the peripheral unit, wherein the owner signal is based on one of the state values such that only the one of the processors indicated as currently owning the peripheral is coupled by the multiplexor to the peripheral.
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Abstract
A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.
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Citations
19 Claims
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1. An embedded computing system, comprising:
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a plurality of processors;
a bus coupling to a plurality of peripheral units;
a multiplexor for coupling each of the plurality of processors to the bus in response to an owner signal; and
a set of peripheral-share registers wherein each member of the set resides at and is associated with a particular one of the plurality of peripheral units and includes an entry holding a state value indicating which of the plurality of processors currently owns the peripheral unit, wherein the owner signal is based on one of the state values such that only the one of the processors indicated as currently owning the peripheral is coupled by the multiplexor to the peripheral. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A multiprocessor controller, comprising:
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first and second processor cores;
a plurality of peripherals;
a bus coupling the processor cores to the peripherals; and
means for arbitrating between the processor cores for communication access to requested ones of the peripherals, whereby each of the peripherals is only used by one of the core processors at a particular time, wherein the arbitrating means comprises logic for determining which of the processor cores is an owner of a requested one of the peripherals, wherein the arbitrating means further comprises a multiplexor for selectably coupling the processor cores to the bus in response to an owner signal, the multiplexor comprising;
an address multiplexor coupled to address outputs of the processor cores wherein the address multiplexor selectively couples one of the processor address outputs to a MUX address output based on a state of the owner signal; and
a data multiplexor coupled to data outputs of the processor cores, wherein the data multiplexor selectively couples one of the processor data outputs to a MUX data output based on the state of the owner signal; and
a set of peripheral-share registers wherein each member of the set resides at and is associated with one of the plurality of peripherals and includes an entry that holds a state value indicating which of the processor cores currently owns the associated peripheral. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A multiprocessor computing system, comprising:
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a pair of processors;
a plurality of peripheral units;
a bus coupling to each of the peripheral units;
a multiplexor selectively coupling each of the processors to the bus, wherein the processors, the peripheral units, and the multiplexor comprise a single integrated circuit, in the integrated circuit, a peripheral register associated with each of the peripheral units including en entry associated with each of the processors holding a state value indicating which one of the processors owns the associated peripheral unit, wherein the multiplexor performs the coupling based on the state values in the peripheral registers. - View Dependent Claims (16, 17, 18, 19)
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Specification